diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4366-drm-amdgpu-change-read-of-GPU-clock-counter-on-Vega1.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4366-drm-amdgpu-change-read-of-GPU-clock-counter-on-Vega1.patch | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4366-drm-amdgpu-change-read-of-GPU-clock-counter-on-Vega1.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4366-drm-amdgpu-change-read-of-GPU-clock-counter-on-Vega1.patch new file mode 100644 index 00000000..47afacc7 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4366-drm-amdgpu-change-read-of-GPU-clock-counter-on-Vega1.patch @@ -0,0 +1,48 @@ +From d471a8a8f117b852f6aa081443747ed8e4b66aa7 Mon Sep 17 00:00:00 2001 +From: Eric Huang <JinhuiEric.Huang@amd.com> +Date: Tue, 5 Nov 2019 16:29:57 -0500 +Subject: [PATCH 4366/4736] drm/amdgpu: change read of GPU clock counter on + Vega10 VF + +Using unified VBIOS has performance drop in sriov environment. +The fix is switching to another register instead. + +Signed-off-by: Eric Huang <JinhuiEric.Huang@amd.com> +Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 19 ++++++++++++++++--- + 1 file changed, 16 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index a3bb662acb1f..4fe3c5ebaf58 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -3887,9 +3887,22 @@ static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev) + uint64_t clock; + + mutex_lock(&adev->gfx.gpu_clock_mutex); +- WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); +- clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) | +- ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); ++ if (adev->asic_type == CHIP_VEGA10 && amdgpu_sriov_runtime(adev)) { ++ uint32_t tmp, lsb, msb, i = 0; ++ do { ++ if (i != 0) ++ udelay(1); ++ tmp = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_MSB); ++ lsb = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_LSB); ++ msb = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_MSB); ++ i++; ++ } while (unlikely(tmp != msb) && (i < adev->usec_timeout)); ++ clock = (uint64_t)lsb | ((uint64_t)msb << 32ULL); ++ } else { ++ WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); ++ clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) | ++ ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); ++ } + mutex_unlock(&adev->gfx.gpu_clock_mutex); + return clock; + } +-- +2.17.1 + |