diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4356-drm-amd-display-Add-some-hardware-status-in-DTN-log-.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4356-drm-amd-display-Add-some-hardware-status-in-DTN-log-.patch | 221 |
1 files changed, 221 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4356-drm-amd-display-Add-some-hardware-status-in-DTN-log-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4356-drm-amd-display-Add-some-hardware-status-in-DTN-log-.patch new file mode 100644 index 00000000..e42c4852 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4356-drm-amd-display-Add-some-hardware-status-in-DTN-log-.patch @@ -0,0 +1,221 @@ +From e2e1baab88fd4354ab464cfe6ed1c5097b8ce421 Mon Sep 17 00:00:00 2001 +From: "Leo (Hanghong) Ma" <hanghong.ma@amd.com> +Date: Fri, 6 Sep 2019 09:49:19 -0400 +Subject: [PATCH 4356/4736] drm/amd/display: Add some hardware status in DTN + log debugfs + +[Why] +For debug purpose, we need to check the following hardware status +in DTN log debugfs: +1.dpp & hubp clock enable; +2.crtc blank enable; +3.link phy status; + +[How] +Add the upper information in the amdgpu_dm_dtn_log debugfs. + +For CRTC blanked status, since DCN2 and greater reports it on the OPP +instead of OTG, we patch it in after calling optc1_read_otg_states. +Ideally, this should be done in the DCN version specific function hooks. +It has been left as a TODO item. + +Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> +Reviewed-by: Mikita Lipski <Mikita.Lipski@amd.com> +Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Acked-by: Harry Wentland <Harry.Wentland@amd.com> +--- + .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 3 ++ + .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 1 + + .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 43 +++++++++++++------ + .../gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 1 + + .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 1 + + .../amd/display/dc/dcn20/dcn20_link_encoder.c | 1 + + .../drm/amd/display/dc/inc/hw/link_encoder.h | 1 + + 7 files changed, 37 insertions(+), 14 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c +index 14d1be6c66e6..5aeee938605a 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c +@@ -1014,6 +1014,9 @@ void hubp1_read_state_common(struct hubp *hubp) + HUBP_TTU_DISABLE, &s->ttu_disable, + HUBP_UNDERFLOW_STATUS, &s->underflow_status); + ++ REG_GET(HUBP_CLK_CNTL, ++ HUBP_CLOCK_ENABLE, &s->clock_en); ++ + REG_GET(DCN_GLOBAL_TTU_CNTL, + MIN_TTU_VBLANK, &s->min_ttu_vblank); + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h +index ae70d9c0aa1d..e65e76f018e4 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h +@@ -670,6 +670,7 @@ struct dcn_hubp_state { + uint32_t sw_mode; + uint32_t dcc_en; + uint32_t blank_en; ++ uint32_t clock_en; + uint32_t underflow_status; + uint32_t ttu_disable; + uint32_t min_ttu_vblank; +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index 6d84239af593..4b6213d3ecbf 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -128,9 +128,8 @@ static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx) + struct resource_pool *pool = dc->res_pool; + int i; + +- DTN_INFO("HUBP: format addr_hi width height" +- " rot mir sw_mode dcc_en blank_en ttu_dis underflow" +- " min_ttu_vblank qos_low_wm qos_high_wm\n"); ++ DTN_INFO( ++ "HUBP: format addr_hi width height rot mir sw_mode dcc_en blank_en clock_en ttu_dis underflow min_ttu_vblank qos_low_wm qos_high_wm\n"); + for (i = 0; i < pool->pipe_count; i++) { + struct hubp *hubp = pool->hubps[i]; + struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state); +@@ -138,8 +137,7 @@ static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx) + hubp->funcs->hubp_read_state(hubp); + + if (!s->blank_en) { +- DTN_INFO("[%2d]: %5xh %6xh %5d %6d %2xh %2xh %6xh" +- " %6d %8d %7d %8xh", ++ DTN_INFO("[%2d]: %5xh %6xh %5d %6d %2xh %2xh %6xh %6d %8d %8d %7d %8xh", + hubp->inst, + s->pixel_format, + s->inuse_addr_hi, +@@ -150,6 +148,7 @@ static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx) + s->sw_mode, + s->dcc_en, + s->blank_en, ++ s->clock_en, + s->ttu_disable, + s->underflow_status); + DTN_INFO_MICRO_SEC(s->min_ttu_vblank); +@@ -307,21 +306,35 @@ void dcn10_log_hw_state(struct dc *dc, + } + DTN_INFO("\n"); + +- DTN_INFO("OTG: v_bs v_be v_ss v_se vpol vmax vmin vmax_sel vmin_sel" +- " h_bs h_be h_ss h_se hpol htot vtot underflow\n"); ++ DTN_INFO("OTG: v_bs v_be v_ss v_se vpol vmax vmin vmax_sel vmin_sel h_bs h_be h_ss h_se hpol htot vtot underflow blank_en\n"); + + for (i = 0; i < pool->timing_generator_count; i++) { + struct timing_generator *tg = pool->timing_generators[i]; + struct dcn_otg_state s = {0}; +- ++ /* Read shared OTG state registers for all DCNx */ + optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s); + ++#ifdef CONFIG_DRM_AMD_DC_DCN2_0 ++ /* ++ * For DCN2 and greater, a register on the OPP is used to ++ * determine if the CRTC is blanked instead of the OTG. So use ++ * dpg_is_blanked() if exists, otherwise fallback on otg. ++ * ++ * TODO: Implement DCN-specific read_otg_state hooks. ++ */ ++ if (pool->opps[i]->funcs->dpg_is_blanked) ++ s.blank_enabled = pool->opps[i]->funcs->dpg_is_blanked(pool->opps[i]); ++ else ++ s.blank_enabled = tg->funcs->is_blanked(tg); ++#else ++ s.blank_enabled = tg->funcs->is_blanked(tg); ++#endif ++ + //only print if OTG master is enabled + if ((s.otg_enabled & 1) == 0) + continue; + +- DTN_INFO("[%d]: %5d %5d %5d %5d %5d %5d %5d %9d %9d %5d %5d %5d" +- " %5d %5d %5d %5d %9d\n", ++ DTN_INFO("[%d]: %5d %5d %5d %5d %5d %5d %5d %9d %9d %5d %5d %5d %5d %5d %5d %5d %9d %8d\n", + tg->inst, + s.v_blank_start, + s.v_blank_end, +@@ -339,7 +352,8 @@ void dcn10_log_hw_state(struct dc *dc, + s.h_sync_a_pol, + s.h_total, + s.v_total, +- s.underflow_occurred_status); ++ s.underflow_occurred_status, ++ s.blank_enabled); + + // Clear underflow for debug purposes + // We want to keep underflow sticky bit on for the longevity tests outside of test environment. +@@ -386,7 +400,7 @@ void dcn10_log_hw_state(struct dc *dc, + } + DTN_INFO("\n"); + +- DTN_INFO("L_ENC: DPHY_FEC_EN DPHY_FEC_READY_SHADOW DPHY_FEC_ACTIVE_STATUS\n"); ++ DTN_INFO("L_ENC: DPHY_FEC_EN DPHY_FEC_READY_SHADOW DPHY_FEC_ACTIVE_STATUS DP_LINK_TRAINING_COMPLETE\n"); + for (i = 0; i < dc->link_count; i++) { + struct link_encoder *lenc = dc->links[i]->link_enc; + +@@ -394,11 +408,12 @@ void dcn10_log_hw_state(struct dc *dc, + + if (lenc->funcs->read_state) { + lenc->funcs->read_state(lenc, &s); +- DTN_INFO("[%-3d]: %-12d %-22d %-22d\n", ++ DTN_INFO("[%-3d]: %-12d %-22d %-22d %-25d\n", + i, + s.dphy_fec_en, + s.dphy_fec_ready_shadow, +- s.dphy_fec_active_status); ++ s.dphy_fec_active_status, ++ s.dp_link_training_complete); + DTN_INFO("\n"); + } + } +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c +index 5be042acf9fa..8249b4429186 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c +@@ -404,6 +404,7 @@ static const struct opp_funcs dcn10_opp_funcs = { + .opp_pipe_clock_control = opp1_pipe_clock_control, + #if defined(CONFIG_DRM_AMD_DC_DCN2_0) + .opp_set_disp_pattern_generator = NULL, ++ .dpg_is_blanked = NULL, + #endif + .opp_destroy = opp1_destroy + }; +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h +index c8d795b335ba..4476bc8cdb4d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h +@@ -542,6 +542,7 @@ struct dcn_otg_state { + uint32_t h_total; + uint32_t underflow_occurred_status; + uint32_t otg_enabled; ++ uint32_t blank_enabled; + }; + + void optc1_read_otg_state(struct optc *optc1, +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c +index e476f27aa3a9..0e0306d84cd8 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c +@@ -203,6 +203,7 @@ void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s) + REG_GET(DP_DPHY_CNTL, DPHY_FEC_EN, &s->dphy_fec_en); + REG_GET(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, &s->dphy_fec_ready_shadow); + REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status); ++ REG_GET(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, &s->dp_link_training_complete); + } + #endif + +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +index b21909216fb6..af57751ed8a1 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +@@ -124,6 +124,7 @@ struct link_enc_state { + uint32_t dphy_fec_en; + uint32_t dphy_fec_ready_shadow; + uint32_t dphy_fec_active_status; ++ uint32_t dp_link_training_complete; + + }; + #endif +-- +2.17.1 + |