diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4323-drm-amdgpu-Add-ucode-support-for-DMCUB.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4323-drm-amdgpu-Add-ucode-support-for-DMCUB.patch | 96 |
1 files changed, 96 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4323-drm-amdgpu-Add-ucode-support-for-DMCUB.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4323-drm-amdgpu-Add-ucode-support-for-DMCUB.patch new file mode 100644 index 00000000..3c934b9a --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4323-drm-amdgpu-Add-ucode-support-for-DMCUB.patch @@ -0,0 +1,96 @@ +From 8d04ab50151f2f903e195a2b0c5d5f6bba03664a Mon Sep 17 00:00:00 2001 +From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> +Date: Tue, 22 Oct 2019 13:07:55 -0400 +Subject: [PATCH 4323/4736] drm/amdgpu: Add ucode support for DMCUB + +The DMCUB is a secondary DMCU (Display MicroController Unit) that has +its own separate firmware. It's required for DMCU support on Renoir. + +Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> +Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 11 ++++++++++- + drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 9 +++++++++ + 2 files changed, 19 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c +index fce1f71c1cff..86cd75ca39d2 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c +@@ -447,6 +447,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, + const struct common_firmware_header *header = NULL; + const struct gfx_firmware_header_v1_0 *cp_hdr = NULL; + const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL; ++ const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL; + + if (NULL == ucode->fw) + return 0; +@@ -460,6 +461,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, + header = (const struct common_firmware_header *)ucode->fw->data; + cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; + dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data; ++ dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data; + + if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP || + (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 && +@@ -470,7 +472,8 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, + ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM && + ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM && + ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_ERAM && +- ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_INTV)) { ++ ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_INTV && ++ ucode->ucode_id != AMDGPU_UCODE_ID_DMCUB)) { + ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes); + + memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + +@@ -506,6 +509,12 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, + le32_to_cpu(header->ucode_array_offset_bytes) + + le32_to_cpu(dmcu_hdr->intv_offset_bytes)), + ucode->ucode_size); ++ } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCUB) { ++ ucode->ucode_size = le32_to_cpu(dmcub_hdr->inst_const_bytes); ++ memcpy(ucode->kaddr, ++ (void *)((uint8_t *)ucode->fw->data + ++ le32_to_cpu(header->ucode_array_offset_bytes)), ++ ucode->ucode_size); + } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL) { + ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes; + memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl, +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h +index 410587b950f3..eaf2d5b9c92f 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h +@@ -251,6 +251,13 @@ struct dmcu_firmware_header_v1_0 { + uint32_t intv_size_bytes; /* size of interrupt vectors, in bytes */ + }; + ++/* version_major=1, version_minor=0 */ ++struct dmcub_firmware_header_v1_0 { ++ struct common_firmware_header header; ++ uint32_t inst_const_bytes; /* size of instruction region, in bytes */ ++ uint32_t bss_data_bytes; /* size of bss/data region, in bytes */ ++}; ++ + /* header is fixed size */ + union amdgpu_firmware_header { + struct common_firmware_header common; +@@ -268,6 +275,7 @@ union amdgpu_firmware_header { + struct sdma_firmware_header_v1_1 sdma_v1_1; + struct gpu_info_firmware_header_v1_0 gpu_info; + struct dmcu_firmware_header_v1_0 dmcu; ++ struct dmcub_firmware_header_v1_0 dmcub; + uint8_t raw[0x100]; + }; + +@@ -307,6 +315,7 @@ enum AMDGPU_UCODE_ID { + AMDGPU_UCODE_ID_DMCU_INTV, + AMDGPU_UCODE_ID_VCN0_RAM, + AMDGPU_UCODE_ID_VCN1_RAM, ++ AMDGPU_UCODE_ID_DMCUB, + AMDGPU_UCODE_ID_MAXIMUM, + }; + +-- +2.17.1 + |