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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4318-drm-amdgpu-gmc10-properly-set-BANK_SELECT-and-FRAGME.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4318-drm-amdgpu-gmc10-properly-set-BANK_SELECT-and-FRAGME.patch62
1 files changed, 62 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4318-drm-amdgpu-gmc10-properly-set-BANK_SELECT-and-FRAGME.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4318-drm-amdgpu-gmc10-properly-set-BANK_SELECT-and-FRAGME.patch
new file mode 100644
index 00000000..b0392615
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4318-drm-amdgpu-gmc10-properly-set-BANK_SELECT-and-FRAGME.patch
@@ -0,0 +1,62 @@
+From e91ddfb275ca28dc49b511edae9bad77b9c4d132 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 29 Oct 2019 17:14:15 -0400
+Subject: [PATCH 4318/4736] drm/amdgpu/gmc10: properly set BANK_SELECT and
+ FRAGMENT_SIZE
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+These were not aligned for optimal performance for GPUVM.
+
+Acked-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Tianci Yin <tianci.yin@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 9 +++++++++
+ drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 9 +++++++++
+ 2 files changed, 18 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+index b601c6740ef5..b4f32d853ca1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+@@ -155,6 +155,15 @@ static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
+ WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp);
+
+ tmp = mmGCVM_L2_CNTL3_DEFAULT;
++ if (adev->gmc.translate_further) {
++ tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
++ tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
++ L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
++ } else {
++ tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
++ tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
++ L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
++ }
+ WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp);
+
+ tmp = mmGCVM_L2_CNTL4_DEFAULT;
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+index 2eea702de8ee..945533634711 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+@@ -142,6 +142,15 @@ static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
+ WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp);
+
+ tmp = mmMMVM_L2_CNTL3_DEFAULT;
++ if (adev->gmc.translate_further) {
++ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
++ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
++ L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
++ } else {
++ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
++ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
++ L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
++ }
+ WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp);
+
+ tmp = mmMMVM_L2_CNTL4_DEFAULT;
+--
+2.17.1
+