diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4237-drm-amd-display-correctly-populate-dpp-refclk-in-fpg.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4237-drm-amd-display-correctly-populate-dpp-refclk-in-fpg.patch | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4237-drm-amd-display-correctly-populate-dpp-refclk-in-fpg.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4237-drm-amd-display-correctly-populate-dpp-refclk-in-fpg.patch new file mode 100644 index 00000000..cbf9be13 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4237-drm-amd-display-correctly-populate-dpp-refclk-in-fpg.patch @@ -0,0 +1,58 @@ +From c1457d444d163b12fd5457314507acce75f9a34a Mon Sep 17 00:00:00 2001 +From: Anthony Koo <Anthony.Koo@amd.com> +Date: Fri, 27 Sep 2019 10:52:15 -0400 +Subject: [PATCH 4237/4736] drm/amd/display: correctly populate dpp refclk in + fpga + +[Why] +In diags environment we are not programming the DPP DTO +correctly. + +[How] +Populate the dpp refclk in dccg so it can be used to correctly +program DPP DTO. + +Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +--- + .../drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 10 ++++++++-- + 1 file changed, 8 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c +index ecd2cb4840e3..69daddbfbf29 100644 +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c +@@ -260,6 +260,8 @@ void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr, + struct dc_state *context, + bool safe_to_lower) + { ++ struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr); ++ + struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; + /* Min fclk = 1.2GHz since all the extra scemi logic seems to run off of it */ + int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000; +@@ -297,14 +299,18 @@ void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr, + clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz; + } + +- /* Both fclk and dppclk ref are run on the same scemi clock so we +- * need to keep the same value for both ++ /* Both fclk and ref_dppclk run on the same scemi clock. ++ * So take the higher value since the DPP DTO is typically programmed ++ * such that max dppclk is 1:1 with ref_dppclk. + */ + if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz) + clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz; + if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz) + clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz; + ++ // Both fclk and ref_dppclk run on the same scemi clock. ++ clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz; ++ + dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks); + } + +-- +2.17.1 + |