diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4172-drm-amd-display-Add-DCN_BASE-regs.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4172-drm-amd-display-Add-DCN_BASE-regs.patch | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4172-drm-amd-display-Add-DCN_BASE-regs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4172-drm-amd-display-Add-DCN_BASE-regs.patch new file mode 100644 index 00000000..8374bd65 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4172-drm-amd-display-Add-DCN_BASE-regs.patch @@ -0,0 +1,64 @@ +From 0fcb1884fb7b2db1e44bbdca280bce9284e3b902 Mon Sep 17 00:00:00 2001 +From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Date: Wed, 2 Oct 2019 11:51:20 -0400 +Subject: [PATCH 4172/4736] drm/amd/display: Add DCN_BASE regs + +Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Reviewed-by: Roman Li <Roman.Li@amd.com> +--- + .../gpu/drm/amd/include/renoir_ip_offset.h | 34 +++++++++++++++++++ + 1 file changed, 34 insertions(+) + +diff --git a/drivers/gpu/drm/amd/include/renoir_ip_offset.h b/drivers/gpu/drm/amd/include/renoir_ip_offset.h +index 094648cac392..07633e22e99a 100644 +--- a/drivers/gpu/drm/amd/include/renoir_ip_offset.h ++++ b/drivers/gpu/drm/amd/include/renoir_ip_offset.h +@@ -169,6 +169,11 @@ static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; ++static const struct IP_BASE DCN_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, ++ { { 0, 0, 0, 0, 0 } }, ++ { { 0, 0, 0, 0, 0 } }, ++ { { 0, 0, 0, 0, 0 } }, ++ { { 0, 0, 0, 0, 0 } } } }; + static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, +@@ -1361,4 +1366,33 @@ static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x0240300 + #define UVD0_BASE__INST6_SEG3 0 + #define UVD0_BASE__INST6_SEG4 0 + ++#define DCN_BASE__INST0_SEG0 0x00000012 ++#define DCN_BASE__INST0_SEG1 0x000000C0 ++#define DCN_BASE__INST0_SEG2 0x000034C0 ++#define DCN_BASE__INST0_SEG3 0 ++#define DCN_BASE__INST0_SEG4 0 ++ ++#define DCN_BASE__INST1_SEG0 0 ++#define DCN_BASE__INST1_SEG1 0 ++#define DCN_BASE__INST1_SEG2 0 ++#define DCN_BASE__INST1_SEG3 0 ++#define DCN_BASE__INST1_SEG4 0 ++ ++#define DCN_BASE__INST2_SEG0 0 ++#define DCN_BASE__INST2_SEG1 0 ++#define DCN_BASE__INST2_SEG2 0 ++#define DCN_BASE__INST2_SEG3 0 ++#define DCN_BASE__INST2_SEG4 0 ++ ++#define DCN_BASE__INST3_SEG0 0 ++#define DCN_BASE__INST3_SEG1 0 ++#define DCN_BASE__INST3_SEG2 0 ++#define DCN_BASE__INST3_SEG3 0 ++#define DCN_BASE__INST3_SEG4 0 ++ ++#define DCN_BASE__INST4_SEG0 0 ++#define DCN_BASE__INST4_SEG1 0 ++#define DCN_BASE__INST4_SEG2 0 ++#define DCN_BASE__INST4_SEG3 0 ++#define DCN_BASE__INST4_SEG4 0 + #endif +-- +2.17.1 + |