diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4168-drm-amd-display-update-register-field-access-mechani.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4168-drm-amd-display-update-register-field-access-mechani.patch | 546 |
1 files changed, 546 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4168-drm-amd-display-update-register-field-access-mechani.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4168-drm-amd-display-update-register-field-access-mechani.patch new file mode 100644 index 00000000..f41a5fc7 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4168-drm-amd-display-update-register-field-access-mechani.patch @@ -0,0 +1,546 @@ +From 40d01f785cf532f60d467345b0f371059017537b Mon Sep 17 00:00:00 2001 +From: abdoulaye berthe <abdoulaye.berthe@amd.com> +Date: Tue, 13 Aug 2019 09:24:10 -0400 +Subject: [PATCH 4168/4736] drm/amd/display: update register field access + mechanism + +1-add timeout length and multiplier fields to aux_control1 register +2-update access mechanism from macro constructed name to uint32_t +defined addresses. +3-define registers and field per asic family + +Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com> +Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Reviewed-by: Roman Li <Roman.Li@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 11 +- + drivers/gpu/drm/amd/display/dc/dce/dce_aux.h | 175 +++++++++++++++++- + .../amd/display/dc/dce100/dce100_resource.c | 12 +- + .../amd/display/dc/dce110/dce110_resource.c | 12 +- + .../amd/display/dc/dce112/dce112_resource.c | 12 +- + .../amd/display/dc/dce120/dce120_resource.c | 12 +- + .../drm/amd/display/dc/dce80/dce80_resource.c | 12 +- + .../drm/amd/display/dc/dcn10/dcn10_resource.c | 12 +- + .../drm/amd/display/dc/dcn20/dcn20_resource.c | 13 +- + .../drm/amd/display/dc/dcn21/dcn21_resource.c | 12 +- + 10 files changed, 271 insertions(+), 12 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c +index 16960ef29132..574447185f4a 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c +@@ -39,6 +39,10 @@ + + #include "reg_helper.h" + ++#undef FN ++#define FN(reg_name, field_name) \ ++ aux110->shift->field_name, aux110->mask->field_name ++ + #define FROM_AUX_ENGINE(ptr) \ + container_of((ptr), struct aux_engine_dce110, base) + +@@ -411,11 +415,14 @@ void dce110_engine_destroy(struct dce_aux **engine) + *engine = NULL; + + } ++ + struct dce_aux *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_engine110, + struct dc_context *ctx, + uint32_t inst, + uint32_t timeout_period, +- const struct dce110_aux_registers *regs) ++ const struct dce110_aux_registers *regs, ++ const struct dce110_aux_registers_mask *mask, ++ const struct dce110_aux_registers_shift *shift) + { + aux_engine110->base.ddc = NULL; + aux_engine110->base.ctx = ctx; +@@ -425,6 +432,8 @@ struct dce_aux *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_engine + aux_engine110->timeout_period = timeout_period; + aux_engine110->regs = regs; + ++ aux_engine110->mask = mask; ++ aux_engine110->shift = shift; + return &aux_engine110->base; + } + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h +index ed7fec8fe253..717378502e9d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h +@@ -29,6 +29,7 @@ + #include "i2caux_interface.h" + #include "inc/hw/aux_engine.h" + ++ + #ifdef CONFIG_DRM_AMD_DC_DCN2_0 + #define AUX_COMMON_REG_LIST0(id)\ + SRI(AUX_CONTROL, DP_AUX, id), \ +@@ -36,6 +37,7 @@ + SRI(AUX_SW_DATA, DP_AUX, id), \ + SRI(AUX_SW_CONTROL, DP_AUX, id), \ + SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \ ++ SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id), \ + SRI(AUX_SW_STATUS, DP_AUX, id) + #endif + +@@ -55,6 +57,7 @@ struct dce110_aux_registers { + uint32_t AUX_SW_DATA; + uint32_t AUX_SW_CONTROL; + uint32_t AUX_INTERRUPT_CONTROL; ++ uint32_t AUX_DPHY_RX_CONTROL1; + uint32_t AUX_SW_STATUS; + uint32_t AUXN_IMPCAL; + uint32_t AUXP_IMPCAL; +@@ -62,6 +65,156 @@ struct dce110_aux_registers { + uint32_t AUX_RESET_MASK; + }; + ++#define DCE_AUX_REG_FIELD_LIST(type)\ ++ type AUX_EN;\ ++ type AUX_RESET;\ ++ type AUX_RESET_DONE;\ ++ type AUX_REG_RW_CNTL_STATUS;\ ++ type AUX_SW_USE_AUX_REG_REQ;\ ++ type AUX_SW_DONE_USING_AUX_REG;\ ++ type AUX_SW_AUTOINCREMENT_DISABLE;\ ++ type AUX_SW_DATA_RW;\ ++ type AUX_SW_INDEX;\ ++ type AUX_SW_GO;\ ++ type AUX_SW_DATA;\ ++ type AUX_SW_REPLY_BYTE_COUNT;\ ++ type AUX_SW_DONE;\ ++ type AUX_SW_DONE_ACK;\ ++ type AUXN_IMPCAL_ENABLE;\ ++ type AUXP_IMPCAL_ENABLE;\ ++ type AUXN_IMPCAL_OVERRIDE_ENABLE;\ ++ type AUXP_IMPCAL_OVERRIDE_ENABLE;\ ++ type AUX_RX_TIMEOUT_LEN;\ ++ type AUX_RX_TIMEOUT_LEN_MUL;\ ++ type AUXN_CALOUT_ERROR_AK;\ ++ type AUXP_CALOUT_ERROR_AK;\ ++ type AUX_SW_START_DELAY;\ ++ type AUX_SW_WR_BYTES ++ ++#define DCE10_AUX_MASK_SH_LIST(mask_sh)\ ++ AUX_SF(AUX_CONTROL, AUX_EN, mask_sh),\ ++ AUX_SF(AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\ ++ AUX_SF(AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\ ++ AUX_SF(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\ ++ AUX_SF(AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\ ++ AUX_SF(AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\ ++ AUX_SF(AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\ ++ AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\ ++ AUX_SF(AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\ ++ AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\ ++ AUX_SF(AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\ ++ AUX_SF(AUX_SW_DATA, AUX_SW_DATA, mask_sh),\ ++ AUX_SF(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\ ++ AUX_SF(AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\ ++ AUX_SF(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\ ++ AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\ ++ AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\ ++ AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\ ++ AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\ ++ AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\ ++ AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh) ++ ++#define DCE_AUX_MASK_SH_LIST(mask_sh)\ ++ AUX_SF(AUX_CONTROL, AUX_EN, mask_sh),\ ++ AUX_SF(AUX_CONTROL, AUX_RESET, mask_sh),\ ++ AUX_SF(AUX_CONTROL, AUX_RESET_DONE, mask_sh),\ ++ AUX_SF(AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\ ++ AUX_SF(AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\ ++ AUX_SF(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\ ++ AUX_SF(AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\ ++ AUX_SF(AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\ ++ AUX_SF(AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\ ++ AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\ ++ AUX_SF(AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\ ++ AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\ ++ AUX_SF(AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\ ++ AUX_SF(AUX_SW_DATA, AUX_SW_DATA, mask_sh),\ ++ AUX_SF(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\ ++ AUX_SF(AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\ ++ AUX_SF(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\ ++ AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\ ++ AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\ ++ AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\ ++ AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\ ++ AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\ ++ AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh) ++ ++#define DCE12_AUX_MASK_SH_LIST(mask_sh)\ ++ AUX_SF(DP_AUX0_AUX_CONTROL, AUX_EN, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET_DONE, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\ ++ AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\ ++ AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\ ++ AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\ ++ AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\ ++ AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\ ++ AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh) ++ ++/* DCN10 MASK */ ++#define DCN10_AUX_MASK_SH_LIST(mask_sh)\ ++ AUX_SF(DP_AUX0_AUX_CONTROL, AUX_EN, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET_DONE, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\ ++ AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\ ++ AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\ ++ AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\ ++ AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\ ++ AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\ ++ AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh) ++ ++/* for all other DCN */ ++#define DCN_AUX_MASK_SH_LIST(mask_sh)\ ++ AUX_SF(DP_AUX0_AUX_CONTROL, AUX_EN, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET_DONE, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN_MUL, mask_sh) ++ ++#define AUX_SF(reg_name, field_name, post_fix)\ ++ .field_name = reg_name ## __ ## field_name ## post_fix ++ + enum { /* This is the timeout as defined in DP 1.2a, + * 2.3.4 "Detailed uPacket TX AUX CH State Description". + */ +@@ -97,17 +250,31 @@ struct dce_aux { + uint32_t max_defer_write_retry; + + bool acquire_reset; ++ const struct dce_aux_funcs *funcs; ++}; ++ ++struct dce110_aux_registers_mask { ++ DCE_AUX_REG_FIELD_LIST(uint32_t); + }; + ++struct dce110_aux_registers_shift { ++ DCE_AUX_REG_FIELD_LIST(uint8_t); ++}; ++ ++ + struct aux_engine_dce110 { + struct dce_aux base; + const struct dce110_aux_registers *regs; ++ const struct dce110_aux_registers_mask *mask; ++ const struct dce110_aux_registers_shift *shift; + struct { + uint32_t aux_control; + uint32_t aux_arb_control; + uint32_t aux_sw_data; + uint32_t aux_sw_control; + uint32_t aux_interrupt_control; ++ uint32_t aux_dphy_rx_control1; ++ uint32_t aux_dphy_rx_control0; + uint32_t aux_sw_status; + } addr; + uint32_t timeout_period; +@@ -120,12 +287,14 @@ struct aux_engine_dce110_init_data { + const struct dce110_aux_registers *regs; + }; + +-struct dce_aux *dce110_aux_engine_construct( +- struct aux_engine_dce110 *aux_engine110, ++struct dce_aux *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_engine110, + struct dc_context *ctx, + uint32_t inst, + uint32_t timeout_period, +- const struct dce110_aux_registers *regs); ++ const struct dce110_aux_registers *regs, ++ ++ const struct dce110_aux_registers_mask *mask, ++ const struct dce110_aux_registers_shift *shift); + + void dce110_engine_destroy(struct dce_aux **engine); + +diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +index 3614e516489f..fe1538ab76ba 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +@@ -534,6 +534,14 @@ static const struct dce_mem_input_mask mi_masks = { + .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK + }; + ++static const struct dce110_aux_registers_shift aux_shift = { ++ DCE10_AUX_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dce110_aux_registers_mask aux_mask = { ++ DCE10_AUX_MASK_SH_LIST(_MASK) ++}; ++ + static struct mem_input *dce100_mem_input_create( + struct dc_context *ctx, + uint32_t inst) +@@ -643,7 +651,9 @@ struct dce_aux *dce100_aux_engine_create( + + dce110_aux_engine_construct(aux_engine, ctx, inst, + SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, +- &aux_engine_regs[inst]); ++ &aux_engine_regs[inst], ++ &aux_mask, ++ &aux_shift); + + return &aux_engine->base; + } +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +index a487b75d23b6..06ecdf044ddc 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +@@ -273,6 +273,14 @@ static const struct dce_stream_encoder_mask se_mask = { + SE_COMMON_MASK_SH_LIST_DCE110(_MASK) + }; + ++static const struct dce110_aux_registers_shift aux_shift = { ++ DCE_AUX_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dce110_aux_registers_mask aux_mask = { ++ DCE_AUX_MASK_SH_LIST(_MASK) ++}; ++ + #define opp_regs(id)\ + [id] = {\ + OPP_DCE_110_REG_LIST(id),\ +@@ -690,7 +698,9 @@ struct dce_aux *dce110_aux_engine_create( + + dce110_aux_engine_construct(aux_engine, ctx, inst, + SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, +- &aux_engine_regs[inst]); ++ &aux_engine_regs[inst], ++ &aux_mask, ++ &aux_shift); + + return &aux_engine->base; + } +diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +index ec67db9c86e8..8dc75f71240d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +@@ -170,6 +170,14 @@ static const struct dce_abm_mask abm_mask = { + ABM_MASK_SH_LIST_DCE110(_MASK) + }; + ++static const struct dce110_aux_registers_shift aux_shift = { ++ DCE_AUX_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dce110_aux_registers_mask aux_mask = { ++ DCE_AUX_MASK_SH_LIST(_MASK) ++}; ++ + #define ipp_regs(id)\ + [id] = {\ + IPP_DCE110_REG_LIST_DCE_BASE(id)\ +@@ -663,7 +671,9 @@ struct dce_aux *dce112_aux_engine_create( + + dce110_aux_engine_construct(aux_engine, ctx, inst, + SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, +- &aux_engine_regs[inst]); ++ &aux_engine_regs[inst], ++ &aux_mask, ++ &aux_shift); + + return &aux_engine->base; + } +diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +index b5b9a74086a0..3aac593f9b2e 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +@@ -291,6 +291,14 @@ static const struct dce_stream_encoder_mask se_mask = { + SE_COMMON_MASK_SH_LIST_DCE120(_MASK) + }; + ++static const struct dce110_aux_registers_shift aux_shift = { ++ DCE12_AUX_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dce110_aux_registers_mask aux_mask = { ++ DCE12_AUX_MASK_SH_LIST(_MASK) ++}; ++ + #define opp_regs(id)\ + [id] = {\ + OPP_DCE_120_REG_LIST(id),\ +@@ -433,7 +441,9 @@ struct dce_aux *dce120_aux_engine_create( + + dce110_aux_engine_construct(aux_engine, ctx, inst, + SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, +- &aux_engine_regs[inst]); ++ &aux_engine_regs[inst], ++ &aux_mask, ++ &aux_shift); + + return &aux_engine->base; + } +diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +index 8e2aa0abf87c..934d8deb95fc 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +@@ -286,6 +286,14 @@ static const struct dce_opp_mask opp_mask = { + OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK) + }; + ++static const struct dce110_aux_registers_shift aux_shift = { ++ DCE10_AUX_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dce110_aux_registers_mask aux_mask = { ++ DCE10_AUX_MASK_SH_LIST(_MASK) ++}; ++ + #define aux_engine_regs(id)\ + [id] = {\ + AUX_COMMON_REG_LIST(id), \ +@@ -520,7 +528,9 @@ struct dce_aux *dce80_aux_engine_create( + + dce110_aux_engine_construct(aux_engine, ctx, inst, + SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, +- &aux_engine_regs[inst]); ++ &aux_engine_regs[inst], ++ &aux_mask, ++ &aux_shift); + + return &aux_engine->base; + } +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +index 4522097e8a26..82dbc00afe54 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +@@ -317,6 +317,14 @@ static const struct dcn10_link_enc_mask le_mask = { + LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK) + }; + ++static const struct dce110_aux_registers_shift aux_shift = { ++ DCN10_AUX_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dce110_aux_registers_mask aux_mask = { ++ DCN10_AUX_MASK_SH_LIST(_MASK) ++}; ++ + #define ipp_regs(id)\ + [id] = {\ + IPP_REG_LIST_DCN10(id),\ +@@ -662,7 +670,9 @@ struct dce_aux *dcn10_aux_engine_create( + + dce110_aux_engine_construct(aux_engine, ctx, inst, + SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, +- &aux_engine_regs[inst]); ++ &aux_engine_regs[inst], ++ &aux_mask, ++ &aux_shift); + + return &aux_engine->base; + } +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +index 968dc5fe4f1b..f2db1fa2eba9 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +@@ -732,6 +732,15 @@ static const struct dcn20_vmid_mask vmid_masks = { + DCN20_VMID_MASK_SH_LIST(_MASK) + }; + ++static const struct dce110_aux_registers_shift aux_shift = { ++ DCN_AUX_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dce110_aux_registers_mask aux_mask = { ++ DCN_AUX_MASK_SH_LIST(_MASK) ++}; ++ ++ + #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + #define dsc_regsDCN20(id)\ + [id] = {\ +@@ -949,7 +958,9 @@ struct dce_aux *dcn20_aux_engine_create( + + dce110_aux_engine_construct(aux_engine, ctx, inst, + SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, +- &aux_engine_regs[inst]); ++ &aux_engine_regs[inst], ++ &aux_mask, ++ &aux_shift); + + return &aux_engine->base; + } +diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +index 2cc93e2e6ec0..dc5d28d002df 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +@@ -628,6 +628,14 @@ static const struct dcn10_stream_enc_registers stream_enc_regs[] = { + stream_enc_regs(4), + }; + ++static const struct dce110_aux_registers_shift aux_shift = { ++ DCN_AUX_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dce110_aux_registers_mask aux_mask = { ++ DCN_AUX_MASK_SH_LIST(_MASK) ++}; ++ + static const struct dcn10_stream_encoder_shift se_shift = { + SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT) + }; +@@ -685,7 +693,9 @@ static struct dce_aux *dcn21_aux_engine_create( + + dce110_aux_engine_construct(aux_engine, ctx, inst, + SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, +- &aux_engine_regs[inst]); ++ &aux_engine_regs[inst], ++ &aux_mask, ++ &aux_shift); + + return &aux_engine->base; + } +-- +2.17.1 + |