aboutsummaryrefslogtreecommitdiffstats
path: root/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4154-drm-amdgpu-add-new-SMU-7.1.3-registers-for-BACO.patch
diff options
context:
space:
mode:
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4154-drm-amdgpu-add-new-SMU-7.1.3-registers-for-BACO.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4154-drm-amdgpu-add-new-SMU-7.1.3-registers-for-BACO.patch44
1 files changed, 44 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4154-drm-amdgpu-add-new-SMU-7.1.3-registers-for-BACO.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4154-drm-amdgpu-add-new-SMU-7.1.3-registers-for-BACO.patch
new file mode 100644
index 00000000..bcb1a5c9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4154-drm-amdgpu-add-new-SMU-7.1.3-registers-for-BACO.patch
@@ -0,0 +1,44 @@
+From a991be32477d0862ec2ca93fc8c63f304570b897 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 15:18:52 -0500
+Subject: [PATCH 4154/4736] drm/amdgpu: add new SMU 7.1.3 registers for BACO
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h | 1 +
+ drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h | 2 ++
+ 2 files changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h
+index f35aba72e640..21da61c398f5 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h
+@@ -52,6 +52,7 @@
+ #define ixCG_SPLL_FUNC_CNTL_5 0xc0500150
+ #define ixCG_SPLL_FUNC_CNTL_6 0xc0500154
+ #define ixCG_SPLL_FUNC_CNTL_7 0xc0500158
++#define ixCG_SPLL_STATUS 0xC050015C
+ #define ixSPLL_CNTL_MODE 0xc0500160
+ #define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164
+ #define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h
+index 481ee6560aa9..f64fe0fbcb32 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h
+@@ -220,6 +220,8 @@
+ #define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19
+ #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff
+ #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0
++#define CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK 0x2
++#define CG_SPLL_STATUS__SPLL_CHG_STATUS__SHIFT 0x1
+ #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1
+ #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0
+ #define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2
+--
+2.17.1
+