diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4114-drm-HDMI-and-DP-specific-HDCP2.2-defines.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4114-drm-HDMI-and-DP-specific-HDCP2.2-defines.patch | 138 |
1 files changed, 138 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4114-drm-HDMI-and-DP-specific-HDCP2.2-defines.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4114-drm-HDMI-and-DP-specific-HDCP2.2-defines.patch new file mode 100644 index 00000000..ec27a9f0 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4114-drm-HDMI-and-DP-specific-HDCP2.2-defines.patch @@ -0,0 +1,138 @@ +From e2eaca86311ae7819b9b62f77287bd1165d0a6f9 Mon Sep 17 00:00:00 2001 +From: Ramalingam C <ramalingam.c@intel.com> +Date: Mon, 29 Oct 2018 15:15:50 +0530 +Subject: [PATCH 4114/4736] drm: HDMI and DP specific HDCP2.2 defines + +This patch adds HDCP register definitions for HDMI and DP HDCP +adaptations. + +HDMI specific HDCP2.2 register definitions are added into drm_hdcp.h, +where as HDCP2.2 register offsets in DPCD offsets are defined at +drm_dp_helper.h. + +v2: + bit_field definitions are replaced by macros. [Tomas and Jani] +v3: + No Changes. +v4: + Comments style and typos are fixed [Uma] +v5: + Fix for macros. +v6: + Adds _MS to the timeouts to represent units [Sean Paul] +v7: + Macro DP_HDCP_2_2_REG_EKH_KM_OFFSET renamed [Uma] + Redundant macro is removed [Uma] + +Signed-off-by: Ramalingam C <ramalingam.c@intel.com> +Reviewed-by: Sean Paul <seanpaul@chromium.org> +Acked-by: Sean Paul <seanpaul@chromium.org> (for merging through drm-intel) +Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> +Link: https://patchwork.freedesktop.org/patch/msgid/1540806351-7137-6-git-send-email-ramalingam.c@intel.com +--- + include/drm/drm_dp_helper.h | 51 +++++++++++++++++++++++++++++++++++++ + include/drm/drm_hdcp.h | 28 ++++++++++++++++++++ + 2 files changed, 79 insertions(+) + +diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h +index b81ec228ab8e..432e93ac3b3c 100644 +--- a/include/drm/drm_dp_helper.h ++++ b/include/drm/drm_dp_helper.h +@@ -913,6 +913,57 @@ + #define DP_AUX_HDCP_KSV_FIFO 0x6802C + #define DP_AUX_HDCP_AINFO 0x6803B + ++/* DP HDCP2.2 parameter offsets in DPCD address space */ ++#define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000 ++#define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008 ++#define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B ++#define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215 ++#define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D ++#define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220 ++#define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 0x692A0 ++#define DP_HDCP_2_2_REG_M_OFFSET 0x692B0 ++#define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0 ++#define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0 ++#define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0 ++#define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8 ++#define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318 ++#define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328 ++#define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330 ++#define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332 ++#define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335 ++#define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345 ++#define DP_HDCP_2_2_REG_V_OFFSET 0x693E0 ++#define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0 ++#define DP_HDCP_2_2_REG_K_OFFSET 0x693F3 ++#define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5 ++#define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473 ++#define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493 ++#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494 ++#define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518 ++ ++/* DP HDCP message start offsets in DPCD address space */ ++#define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET ++#define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET ++#define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKPUB_KM_OFFSET ++#define DP_HDCP_2_2_AKE_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET ++#define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET DP_HDCP_2_2_REG_HPRIME_OFFSET ++#define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \ ++ DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET ++#define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET ++#define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET DP_HDCP_2_2_REG_LPRIME_OFFSET ++#define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET DP_HDCP_2_2_REG_EDKEY_KS_OFFSET ++#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET DP_HDCP_2_2_REG_RXINFO_OFFSET ++#define DP_HDCP_2_2_REP_SEND_ACK_OFFSET DP_HDCP_2_2_REG_V_OFFSET ++#define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET ++#define DP_HDCP_2_2_REP_STREAM_READY_OFFSET DP_HDCP_2_2_REG_MPRIME_OFFSET ++ ++#define HDCP_2_2_DP_RXSTATUS_LEN 1 ++#define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0)) ++#define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) ((x) & BIT(1)) ++#define HDCP_2_2_DP_RXSTATUS_PAIRING(x) ((x) & BIT(2)) ++#define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3)) ++#define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) ((x) & BIT(4)) ++ + /* DP 1.2 Sideband message defines */ + /* peer device type - DP 1.2a Table 2-92 */ + #define DP_PEER_DEVICE_NONE 0x0 +diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h +index 98e63d870139..5e93faaa7015 100644 +--- a/include/drm/drm_hdcp.h ++++ b/include/drm/drm_hdcp.h +@@ -38,4 +38,32 @@ + #define DRM_HDCP_DDC_BSTATUS 0x41 + #define DRM_HDCP_DDC_KSV_FIFO 0x43 + ++/* HDCP2.2 TIMEOUTs in mSec */ ++#define HDCP_2_2_CERT_TIMEOUT_MS 100 ++#define HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS 1000 ++#define HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS 200 ++#define HDCP_2_2_PAIRING_TIMEOUT_MS 200 ++#define HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS 20 ++#define HDCP_2_2_DP_LPRIME_TIMEOUT_MS 7 ++#define HDCP_2_2_RECVID_LIST_TIMEOUT_MS 3000 ++#define HDCP_2_2_STREAM_READY_TIMEOUT_MS 100 ++ ++/* HDMI HDCP2.2 Register Offsets */ ++#define HDCP_2_2_HDMI_REG_VER_OFFSET 0x50 ++#define HDCP_2_2_HDMI_REG_WR_MSG_OFFSET 0x60 ++#define HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET 0x70 ++#define HDCP_2_2_HDMI_REG_RD_MSG_OFFSET 0x80 ++#define HDCP_2_2_HDMI_REG_DBG_OFFSET 0xC0 ++ ++#define HDCP_2_2_HDMI_SUPPORT_MASK BIT(2) ++#define HDCP_2_2_RX_CAPS_VERSION_VAL 0x02 ++#define HDCP_2_2_SEQ_NUM_MAX 0xFFFFFF ++#define HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN 200 ++ ++/* Below macros take a byte at a time and mask the bit(s) */ ++#define HDCP_2_2_HDMI_RXSTATUS_LEN 2 ++#define HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(x) ((x) & 0x3) ++#define HDCP_2_2_HDMI_RXSTATUS_READY(x) ((x) & BIT(2)) ++#define HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3)) ++ + #endif +-- +2.17.1 + |