diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4092-drm-amdgpu-expand-the-emit-tmz-interface-with-truste.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4092-drm-amdgpu-expand-the-emit-tmz-interface-with-truste.patch | 136 |
1 files changed, 136 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4092-drm-amdgpu-expand-the-emit-tmz-interface-with-truste.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4092-drm-amdgpu-expand-the-emit-tmz-interface-with-truste.patch new file mode 100644 index 00000000..4ef6f052 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4092-drm-amdgpu-expand-the-emit-tmz-interface-with-truste.patch @@ -0,0 +1,136 @@ +From 989ed3ab67eeac447326db39a90c1b5e0fadc0c6 Mon Sep 17 00:00:00 2001 +From: Huang Rui <ray.huang@amd.com> +Date: Thu, 8 Aug 2019 19:07:19 +0800 +Subject: [PATCH 4092/4256] drm/amdgpu: expand the emit tmz interface with + trusted flag +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This patch expands the emit_tmz function to support trusted flag while we want +to set command buffer in trusted mode. + +Signed-off-by: Huang Rui <ray.huang@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Acked-by: Christian König <christian.koenig@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 +- + drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 4 ++-- + drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 16 ++++++++++++---- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 13 ++++++++++--- + 4 files changed, 25 insertions(+), 10 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +index 0515f7a98a11..19e638af4d9c 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +@@ -238,7 +238,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, + } + + if (ring->funcs->emit_tmz) +- amdgpu_ring_emit_tmz(ring, false); ++ amdgpu_ring_emit_tmz(ring, false, false); + + #ifdef CONFIG_X86_64 + if (!(adev->flags & AMD_IS_APU)) +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +index 930316e60155..34aa63ad5799 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +@@ -166,7 +166,7 @@ struct amdgpu_ring_funcs { + void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring, + uint32_t reg0, uint32_t reg1, + uint32_t ref, uint32_t mask); +- void (*emit_tmz)(struct amdgpu_ring *ring, bool start); ++ void (*emit_tmz)(struct amdgpu_ring *ring, bool start, bool trusted); + /* priority functions */ + void (*set_priority) (struct amdgpu_ring *ring, + enum drm_sched_priority priority); +@@ -247,7 +247,7 @@ struct amdgpu_ring { + #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) + #define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m)) + #define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m)) +-#define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b)) ++#define amdgpu_ring_emit_tmz(r, b, s) (r)->funcs->emit_tmz((r), (b), (s)) + #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) + #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) + #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +index 1df3a835e62f..5a153d3893d8 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +@@ -248,7 +248,8 @@ static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); + static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); + static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); + static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); +-static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start); ++static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start, ++ bool trusted); + + static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) + { +@@ -4548,7 +4549,7 @@ static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flag + gfx_v10_0_ring_emit_ce_meta(ring, + flags & AMDGPU_IB_PREEMPTED ? true : false); + +- gfx_v10_0_ring_emit_tmz(ring, true); ++ gfx_v10_0_ring_emit_tmz(ring, true, false); + + dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ + if (flags & AMDGPU_HAVE_CTX_SWITCH) { +@@ -4706,10 +4707,17 @@ static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) + sizeof(de_payload) >> 2); + } + +-static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start) ++static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start, ++ bool trusted) + { + amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); +- amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */ ++ /* ++ * cmd = 0: frame begin ++ * cmd = 1: frame end ++ */ ++ amdgpu_ring_write(ring, ++ ((ring->adev->tmz.enabled && trusted) ? FRAME_TMZ : 0) ++ | FRAME_CMD(start ? 0 : 1)); + } + + static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg) +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index 5f7956004627..b1ff036e9fb5 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -5036,10 +5036,17 @@ static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring) + amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2); + } + +-static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start) ++static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start, ++ bool trusted) + { + amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); +- amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */ ++ /* ++ * cmd = 0: frame begin ++ * cmd = 1: frame end ++ */ ++ amdgpu_ring_write(ring, ++ ((ring->adev->tmz.enabled && trusted) ? FRAME_TMZ : 0) ++ | FRAME_CMD(start ? 0 : 1)); + } + + static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) +@@ -5049,7 +5056,7 @@ static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) + if (amdgpu_sriov_vf(ring->adev)) + gfx_v9_0_ring_emit_ce_meta(ring); + +- gfx_v9_0_ring_emit_tmz(ring, true); ++ gfx_v9_0_ring_emit_tmz(ring, true, false); + + dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ + if (flags & AMDGPU_HAVE_CTX_SWITCH) { +-- +2.17.1 + |