diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4074-drm-amd-display-use-vbios-message-to-call-smu-for-dp.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4074-drm-amd-display-use-vbios-message-to-call-smu-for-dp.patch | 102 |
1 files changed, 102 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4074-drm-amd-display-use-vbios-message-to-call-smu-for-dp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4074-drm-amd-display-use-vbios-message-to-call-smu-for-dp.patch new file mode 100644 index 00000000..7cbf5340 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4074-drm-amd-display-use-vbios-message-to-call-smu-for-dp.patch @@ -0,0 +1,102 @@ +From d00b78c7269671f69ede1af2b9bf32ad3a82e932 Mon Sep 17 00:00:00 2001 +From: Charlene Liu <charlene.liu@amd.com> +Date: Tue, 17 Sep 2019 20:28:40 -0400 +Subject: [PATCH 4074/4256] drm/amd/display: use vbios message to call smu for + dpm level + +[Description] +use vbios message to call smu for dpm level +also only program dmdata in vsyncflip as HW requirement. + +Signed-off-by: Charlene Liu <charlene.liu@amd.com> +Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +--- + .../amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h | 1 + + drivers/gpu/drm/amd/display/dc/dc.h | 8 ++++++++ + .../gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 6 ++++-- + .../drm/amd/display/dc/inc/hw/clk_mgr_internal.h | 15 +++++++++++++++ + 4 files changed, 28 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h +index ac31a9787305..c9fd824f3c23 100644 +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h +@@ -50,4 +50,5 @@ void dcn2_get_clock(struct clk_mgr *clk_mgr, + enum dc_clock_type clock_type, + struct dc_clock_config *clock_cfg); + ++void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr); + #endif //__DCN20_CLK_MGR_H__ +diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h +index 6c50d5c24658..c04a1f40e0be 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc.h ++++ b/drivers/gpu/drm/amd/display/dc/dc.h +@@ -245,6 +245,13 @@ enum wm_report_mode { + WM_REPORT_DEFAULT = 0, + WM_REPORT_OVERRIDE = 1, + }; ++enum dtm_pstate{ ++ dtm_level_p0 = 0,/*highest voltage*/ ++ dtm_level_p1, ++ dtm_level_p2, ++ dtm_level_p3, ++ dtm_level_p4,/*when active_display_count = 0*/ ++}; + + enum dcn_pwr_state { + DCN_PWR_STATE_OPTIMIZED = 0, +@@ -271,6 +278,7 @@ struct dc_clocks { + * optimization required + */ + bool prev_p_state_change_support; ++ enum dtm_pstate dtm_level; + int max_supported_dppclk_khz; + int max_supported_dispclk_khz; + int bw_dppclk_khz; /*a copy of dppclk_khz*/ +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +index 2dce3e4b5e51..ce2530509e12 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +@@ -2209,8 +2209,10 @@ static void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) + link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, + pipe_ctx->stream_res.stream_enc->id, true); + +- if (link->dc->hwss.program_dmdata_engine) +- link->dc->hwss.program_dmdata_engine(pipe_ctx); ++ if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) { ++ if (link->dc->hwss.program_dmdata_engine) ++ link->dc->hwss.program_dmdata_engine(pipe_ctx); ++ } + + link->dc->hwss.update_info_frame(pipe_ctx); + +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h +index 7dd46eb96d67..2e8cd7956a17 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h +@@ -184,6 +184,21 @@ struct clk_mgr_registers { + uint32_t MP1_SMN_C2PMSG_91; + }; + ++enum clock_type { ++ clock_type_dispclk = 1, ++ clock_type_dcfclk, ++ clock_type_socclk, ++ clock_type_pixelclk, ++ clock_type_phyclk, ++ clock_type_dppclk, ++ clock_type_fclk, ++ clock_type_dcfdsclk, ++ clock_type_dscclk, ++ clock_type_uclk, ++ clock_type_dramclk, ++}; ++ ++ + struct state_dependent_clocks { + int display_clk_khz; + int pixel_clk_khz; +-- +2.17.1 + |