1 files changed, 40 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4062-drm-amd-display-wait-for-set-pipe-mcp-command-comple.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4062-drm-amd-display-wait-for-set-pipe-mcp-command-comple.patch
new file mode 100644
index 00000000..e1e7a24d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4062-drm-amd-display-wait-for-set-pipe-mcp-command-comple.patch
@@ -0,0 +1,40 @@
+From 707206a946b412b24b42c67588a02a76e25cd6a1 Mon Sep 17 00:00:00 2001
+From: Josip Pavic <Josip.Pavic@amd.com>
+Date: Thu, 12 Sep 2019 15:40:08 -0400
+Subject: [PATCH 4062/4256] drm/amd/display: wait for set pipe mcp command
+ completion
+
+[Why]
+When the driver sends a pipe set command to the DMCU FW, it does not wait
+for the command to complete. This can lead to unpredictable behavior if,
+for example, the driver were to request a pipe disable to the FW via MCP,
+then power down some hardware before the firmware has completed processing
+the command.
+
+[How]
+Wait for the DMCU FW to finish processing set pipe commands
+
+Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
+index b5c97b313c54..4a22b50bd38a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
+@@ -75,6 +75,9 @@ static bool dce_abm_set_pipe(struct abm *abm, uint32_t controller_id)
+ 	/* notifyDMCUMsg */
+ 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
+ 
++	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
++			1, 80000);
++
+ 	return true;
+ }
+ 
+-- 
+2.17.1
+