diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4057-drm-amd-display-check-phy-dpalt-lane-count-config.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4057-drm-amd-display-check-phy-dpalt-lane-count-config.patch | 120 |
1 files changed, 120 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4057-drm-amd-display-check-phy-dpalt-lane-count-config.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4057-drm-amd-display-check-phy-dpalt-lane-count-config.patch new file mode 100644 index 00000000..4b5fdc85 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4057-drm-amd-display-check-phy-dpalt-lane-count-config.patch @@ -0,0 +1,120 @@ +From 0c542eaba5d96996e04bf61828430f1a9ab6fa87 Mon Sep 17 00:00:00 2001 +From: Lewis Huang <Lewis.Huang@amd.com> +Date: Thu, 5 Sep 2019 15:33:58 +0800 +Subject: [PATCH 4057/4256] drm/amd/display: check phy dpalt lane count config + +[Why] +Type-c PHY config is not align with dpcd lane count. +When those values didn't match, it cause driver do +link training with 4 lane but phy only can output 2 lane. +The link trainig always fail. + +[How] +1. Modify get_max_link_cap function. According DPALT_DP4 +to update max lane count. +2. Add dp_mst_verify_link_cap to handle MST case because +we didn't call dp_mst_verify_link_cap for MST case. + +Signed-off-by: Lewis Huang <Lewis.Huang@amd.com> +Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> +Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +--- + drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 ++- + drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 16 ++++++++++++++++ + .../amd/display/dc/dcn10/dcn10_link_encoder.h | 1 + + drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h | 3 +++ + .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h | 4 ++++ + 5 files changed, 26 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c +index 80ddde0f0262..f352f6028293 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c +@@ -870,7 +870,8 @@ bool dc_link_detect_helper(struct dc_link *link, enum dc_detect_reason reason) + * empty which leads to allocate_mst_payload() has "0" + * pbn_per_slot value leading to exception on dc_fixpt_div() + */ +- link->verified_link_cap = link->reported_link_cap; ++ dp_verify_mst_link_cap(link); ++ + if (prev_sink != NULL) + dc_sink_release(prev_sink); + return false; +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +index 7c78caf7a602..701b73926616 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +@@ -1409,6 +1409,9 @@ static struct dc_link_settings get_max_link_cap(struct dc_link *link) + if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE) + max_link_cap.link_rate = LINK_RATE_HIGH3; + ++ if (link->link_enc->funcs->get_max_link_cap) ++ link->link_enc->funcs->get_max_link_cap(link->link_enc, &max_link_cap); ++ + /* Lower link settings based on sink's link cap */ + if (link->reported_link_cap.lane_count < max_link_cap.lane_count) + max_link_cap.lane_count = +@@ -1670,6 +1673,19 @@ bool dp_verify_link_cap_with_retries( + return success; + } + ++bool dp_verify_mst_link_cap( ++ struct dc_link *link) ++{ ++ struct dc_link_settings max_link_cap = {0}; ++ ++ max_link_cap = get_max_link_cap(link); ++ link->verified_link_cap = get_common_supported_link_settings( ++ link->reported_link_cap, ++ max_link_cap); ++ ++ return true; ++} ++ + static struct dc_link_settings get_common_supported_link_settings( + struct dc_link_settings link_setting_a, + struct dc_link_settings link_setting_b) +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h +index 8bf5f0f2301d..0c12395cfa36 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h +@@ -337,6 +337,7 @@ struct dcn10_link_enc_registers { + type RDPCS_TX_FIFO_ERROR_MASK;\ + type RDPCS_DPALT_DISABLE_TOGGLE_MASK;\ + type RDPCS_DPALT_4LANE_TOGGLE_MASK;\ ++ type RDPCS_PHY_DPALT_DP4;\ + type RDPCS_PHY_DPALT_DISABLE;\ + type RDPCS_PHY_DPALT_DISABLE_ACK;\ + type RDPCS_PHY_DP_MPLLB_V2I;\ +diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h +index 08a4df2c61a8..967706e7898e 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h +@@ -43,6 +43,9 @@ bool dp_verify_link_cap_with_retries( + struct dc_link_settings *known_limit_link_setting, + int attempts); + ++bool dp_verify_mst_link_cap( ++ struct dc_link *link); ++ + bool dp_validate_mode_timing( + struct dc_link *link, + const struct dc_crtc_timing *timing); +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +index abb4e4237fb6..b21909216fb6 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +@@ -184,6 +184,10 @@ struct link_encoder_funcs { + bool (*fec_is_active)(struct link_encoder *enc); + #endif + bool (*is_in_alt_mode) (struct link_encoder *enc); ++ ++ void (*get_max_link_cap)(struct link_encoder *enc, ++ struct dc_link_settings *link_settings); ++ + enum signal_type (*get_dig_mode)( + struct link_encoder *enc); + }; +-- +2.17.1 + |