diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4048-drm-amd-display-Update-V_UPDATE-whenever-VSTARTUP-ch.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4048-drm-amd-display-Update-V_UPDATE-whenever-VSTARTUP-ch.patch | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4048-drm-amd-display-Update-V_UPDATE-whenever-VSTARTUP-ch.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4048-drm-amd-display-Update-V_UPDATE-whenever-VSTARTUP-ch.patch new file mode 100644 index 00000000..2a9f6b39 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4048-drm-amd-display-Update-V_UPDATE-whenever-VSTARTUP-ch.patch @@ -0,0 +1,68 @@ +From 6c748dfa834d882b61f5aaedddb7b9456f63efb0 Mon Sep 17 00:00:00 2001 +From: Aric Cyr <aric.cyr@amd.com> +Date: Fri, 6 Sep 2019 16:24:54 -0400 +Subject: [PATCH 4048/4256] drm/amd/display: Update V_UPDATE whenever VSTARTUP + changes + +[Why] +If VSTARTUP changes due to bandwidth requirements, we must +recalculate and update VLINE2 as well for proper flip reporting. + +[How] +After all calls to program_global_sync which reconfigures +VSTARTUP, also make sure to update V_UPDATE (i.e. VLINE2 on DCNx). + +Signed-off-by: Aric Cyr <aric.cyr@amd.com> +Reviewed-by: Sivapiriyan Kumarasamy <Sivapiriyan.Kumarasamy@amd.com> +Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 +++- + drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 7 +++++++ + 2 files changed, 10 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index 78dbd17d3573..3b55716bf63b 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -2509,8 +2509,10 @@ static void program_all_pipe_in_tree( + pipe_ctx->stream_res.tg->funcs->set_vtg_params( + pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); + +- dc->hwss.blank_pixel_data(dc, pipe_ctx, blank); ++ if (dc->hwss.setup_vupdate_interrupt) ++ dc->hwss.setup_vupdate_interrupt(pipe_ctx); + ++ dc->hwss.blank_pixel_data(dc, pipe_ctx, blank); + } + + if (pipe_ctx->plane_state != NULL) +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +index 84aae9c05781..1b4aac185f3f 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +@@ -1370,6 +1370,9 @@ static void dcn20_program_pipe( + + pipe_ctx->stream_res.tg->funcs->set_vtg_params( + pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); ++ ++ if (dc->hwss.setup_vupdate_interrupt) ++ dc->hwss.setup_vupdate_interrupt(pipe_ctx); + } + + if (pipe_ctx->update_flags.bits.odm) +@@ -1581,8 +1584,12 @@ bool dcn20_update_bandwidth( + + pipe_ctx->stream_res.tg->funcs->set_vtg_params( + pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); ++ + if (pipe_ctx->prev_odm_pipe == NULL) + dc->hwss.blank_pixel_data(dc, pipe_ctx, blank); ++ ++ if (dc->hwss.setup_vupdate_interrupt) ++ dc->hwss.setup_vupdate_interrupt(pipe_ctx); + } + + pipe_ctx->plane_res.hubp->funcs->hubp_setup( +-- +2.17.1 + |