diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4041-drm-amdgpu-Clean-up-gmc_v9_0_gart_enable.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4041-drm-amdgpu-Clean-up-gmc_v9_0_gart_enable.patch | 133 |
1 files changed, 133 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4041-drm-amdgpu-Clean-up-gmc_v9_0_gart_enable.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4041-drm-amdgpu-Clean-up-gmc_v9_0_gart_enable.patch new file mode 100644 index 00000000..ed00bfa5 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4041-drm-amdgpu-Clean-up-gmc_v9_0_gart_enable.patch @@ -0,0 +1,133 @@ +From c6e54732f0548998dea2e134966781de6a275ca8 Mon Sep 17 00:00:00 2001 +From: Oak Zeng <Oak.Zeng@amd.com> +Date: Mon, 7 Oct 2019 15:21:03 -0500 +Subject: [PATCH 4041/4256] drm/amdgpu: Clean up gmc_v9_0_gart_enable + +Many logic in this function are HDP set up, +not gart set up. Moved those logic to gmc_v9_0_hw_init. +No functional change. + +Change-Id: Ib00cc1ffd1e486e77571796dce53aa7506c0c55f +Acked-by: Christian konig <christian.koenig@amd.com> +Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 82 +++++++++++++-------------- + 1 file changed, 41 insertions(+), 41 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +index b5ecc12cfea2..cfe135544d24 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +@@ -1147,13 +1147,7 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) + */ + static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) + { +- int r, i; +- bool value; +- u32 tmp; +- +- amdgpu_device_program_register_sequence(adev, +- golden_settings_vega10_hdp, +- ARRAY_SIZE(golden_settings_vega10_hdp)); ++ int r; + + if (adev->gart.bo == NULL) { + dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); +@@ -1163,15 +1157,6 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) + if (r) + return r; + +- switch (adev->asic_type) { +- case CHIP_RAVEN: +- /* TODO for renoir */ +- mmhub_v1_0_update_power_gating(adev, true); +- break; +- default: +- break; +- } +- + r = gfxhub_v1_0_gart_enable(adev); + if (r) + return r; +@@ -1183,6 +1168,46 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) + if (r) + return r; + ++ DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", ++ (unsigned)(adev->gmc.gart_size >> 20), ++ (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); ++ adev->gart.ready = true; ++ return 0; ++} ++ ++static int gmc_v9_0_hw_init(void *handle) ++{ ++ struct amdgpu_device *adev = (struct amdgpu_device *)handle; ++ bool value; ++ int r, i; ++ u32 tmp; ++ ++ /* The sequence of these two function calls matters.*/ ++ gmc_v9_0_init_golden_registers(adev); ++ ++ if (adev->mode_info.num_crtc) { ++ if (adev->asic_type != CHIP_ARCTURUS) { ++ /* Lockout access through VGA aperture*/ ++ WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); ++ ++ /* disable VGA render */ ++ WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); ++ } ++ } ++ ++ amdgpu_device_program_register_sequence(adev, ++ golden_settings_vega10_hdp, ++ ARRAY_SIZE(golden_settings_vega10_hdp)); ++ ++ switch (adev->asic_type) { ++ case CHIP_RAVEN: ++ /* TODO for renoir */ ++ mmhub_v1_0_update_power_gating(adev, true); ++ break; ++ default: ++ break; ++ } ++ + WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); + + tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL); +@@ -1211,31 +1236,6 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) + if (adev->umc.funcs && adev->umc.funcs->init_registers) + adev->umc.funcs->init_registers(adev); + +- DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", +- (unsigned)(adev->gmc.gart_size >> 20), +- (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); +- adev->gart.ready = true; +- return 0; +-} +- +-static int gmc_v9_0_hw_init(void *handle) +-{ +- int r; +- struct amdgpu_device *adev = (struct amdgpu_device *)handle; +- +- /* The sequence of these two function calls matters.*/ +- gmc_v9_0_init_golden_registers(adev); +- +- if (adev->mode_info.num_crtc) { +- if (adev->asic_type != CHIP_ARCTURUS) { +- /* Lockout access through VGA aperture*/ +- WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); +- +- /* disable VGA render */ +- WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); +- } +- } +- + r = gmc_v9_0_gart_enable(adev); + + return r; +-- +2.17.1 + |