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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4020-drm-amdgpu-Export-setup_vm_pt_regs-logic-for-mmhub-2.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4020-drm-amdgpu-Export-setup_vm_pt_regs-logic-for-mmhub-2.patch68
1 files changed, 68 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4020-drm-amdgpu-Export-setup_vm_pt_regs-logic-for-mmhub-2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4020-drm-amdgpu-Export-setup_vm_pt_regs-logic-for-mmhub-2.patch
new file mode 100644
index 00000000..f27231d0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4020-drm-amdgpu-Export-setup_vm_pt_regs-logic-for-mmhub-2.patch
@@ -0,0 +1,68 @@
+From 74875a8bb5b92463c8d15e51e90cfe67d847d8a5 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Tue, 24 Sep 2019 17:23:12 -0400
+Subject: [PATCH 4020/4256] drm/amdgpu: Export setup_vm_pt_regs() logic for
+ mmhub 2.0
+
+The KFD code will call this function later.
+
+Change-Id: I5993323603799963e9eb473852b6c72de2172ed6
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 19 ++++++++++++-------
+ drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.h | 2 ++
+ 2 files changed, 14 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+index 86ed8cb915a8..2eea702de8ee 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+@@ -31,20 +31,25 @@
+
+ #include "soc15_common.h"
+
+-static void mmhub_v2_0_init_gart_pt_regs(struct amdgpu_device *adev)
++void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
++ uint64_t page_table_base)
+ {
+- uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo);
++ /* two registers distance between mmMMVM_CONTEXT0_* to mmMMVM_CONTEXT1_* */
++ int offset = mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
++ - mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
+
+- WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
+- lower_32_bits(value));
++ WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
++ offset * vmid, lower_32_bits(page_table_base));
+
+- WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
+- upper_32_bits(value));
++ WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
++ offset * vmid, upper_32_bits(page_table_base));
+ }
+
+ static void mmhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev)
+ {
+- mmhub_v2_0_init_gart_pt_regs(adev);
++ uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
++
++ mmhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base);
+
+ WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
+ (u32)(adev->gmc.gart_start >> 12));
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.h b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.h
+index db16f3ece218..3ea4344f0315 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.h
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.h
+@@ -31,5 +31,7 @@ void mmhub_v2_0_init(struct amdgpu_device *adev);
+ int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
+ enum amd_clockgating_state state);
+ void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags);
++void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
++ uint64_t page_table_base);
+
+ #endif
+--
+2.17.1
+