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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4019-drm-amdgpu-Add-the-HDP-flush-support-for-Navi.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4019-drm-amdgpu-Add-the-HDP-flush-support-for-Navi.patch92
1 files changed, 92 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4019-drm-amdgpu-Add-the-HDP-flush-support-for-Navi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4019-drm-amdgpu-Add-the-HDP-flush-support-for-Navi.patch
new file mode 100644
index 00000000..1a090d73
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4019-drm-amdgpu-Add-the-HDP-flush-support-for-Navi.patch
@@ -0,0 +1,92 @@
+From e3d39c2c179e85298a7f9d75e047b45fceacca77 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Fri, 27 Sep 2019 23:30:05 -0400
+Subject: [PATCH 4019/4256] drm/amdgpu: Add the HDP flush support for Navi
+
+The HDP flush support code was missing in the nbio and nv files.
+
+Change-Id: I046ff52567676b56bf16dc1728b02481233acb61
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 16 +++++++++++++---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 9 +++++++++
+ 2 files changed, 22 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+index a5fa741e4aff..f3a5276ce803 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+@@ -27,11 +27,21 @@
+ #include "nbio/nbio_2_3_default.h"
+ #include "nbio/nbio_2_3_offset.h"
+ #include "nbio/nbio_2_3_sh_mask.h"
++#include <uapi/linux/kfd_ioctl.h>
+
+ #define smnPCIE_CONFIG_CNTL 0x11180044
+ #define smnCPM_CONTROL 0x11180460
+ #define smnPCIE_CNTL2 0x11180070
+
++
++static void nbio_v2_3_remap_hdp_registers(struct amdgpu_device *adev)
++{
++ WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
++ adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
++ WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
++ adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
++}
++
+ static u32 nbio_v2_3_get_rev_id(struct amdgpu_device *adev)
+ {
+ u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
+@@ -56,10 +66,9 @@ static void nbio_v2_3_hdp_flush(struct amdgpu_device *adev,
+ struct amdgpu_ring *ring)
+ {
+ if (!ring || !ring->funcs->emit_wreg)
+- WREG32_SOC15_NO_KIQ(NBIO, 0, mmBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL, 0);
++ WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
+ else
+- amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
+- NBIO, 0, mmBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL), 0);
++ amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
+ }
+
+ static u32 nbio_v2_3_get_memsize(struct amdgpu_device *adev)
+@@ -330,4 +339,5 @@ const struct amdgpu_nbio_funcs nbio_v2_3_funcs = {
+ .ih_control = nbio_v2_3_ih_control,
+ .init_registers = nbio_v2_3_init_registers,
+ .detect_hw_virt = nbio_v2_3_detect_hw_virt,
++ .remap_hdp_registers = nbio_v2_3_remap_hdp_registers,
+ };
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index fb097aa089da..994198ef853a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -586,8 +586,11 @@ static const struct amdgpu_asic_funcs nv_asic_funcs =
+
+ static int nv_common_early_init(void *handle)
+ {
++#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
++ adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
++ adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
+ adev->smc_rreg = NULL;
+ adev->smc_wreg = NULL;
+ adev->pcie_rreg = &nv_pcie_rreg;
+@@ -713,6 +716,12 @@ static int nv_common_hw_init(void *handle)
+ nv_program_aspm(adev);
+ /* setup nbio registers */
+ adev->nbio.funcs->init_registers(adev);
++ /* remap HDP registers to a hole in mmio space,
++ * for the purpose of expose those registers
++ * to process space
++ */
++ if (adev->nbio.funcs->remap_hdp_registers)
++ adev->nbio.funcs->remap_hdp_registers(adev);
+ /* enable the doorbell aperture */
+ nv_enable_doorbell_aperture(adev, true);
+
+--
+2.17.1
+