diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4001-drm-amd-amdgpu-sriov-ip-block-setting-of-Arcturus.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4001-drm-amd-amdgpu-sriov-ip-block-setting-of-Arcturus.patch | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4001-drm-amd-amdgpu-sriov-ip-block-setting-of-Arcturus.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4001-drm-amd-amdgpu-sriov-ip-block-setting-of-Arcturus.patch new file mode 100644 index 00000000..6cd05670 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4001-drm-amd-amdgpu-sriov-ip-block-setting-of-Arcturus.patch @@ -0,0 +1,77 @@ +From 1f2686376d9ec1ae178068f29b5b21c3080a447e Mon Sep 17 00:00:00 2001 +From: Jack Zhang <Jack.Zhang1@amd.com> +Date: Thu, 26 Sep 2019 15:24:55 +0800 +Subject: [PATCH 4001/4256] drm/amd/amdgpu/sriov ip block setting of Arcturus + +Add ip block setting for Arcturus SRIOV + +1.PSP need to be initialized before IH. +2.SMU doesn't need to be initialized at kmd driver. +3.Arcturus doesn't support DCE hardware,it needs to skip + register access to DCE. + +Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com> +Reviewed-by: Le Ma <Le.Ma@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 10 ++++++---- + drivers/gpu/drm/amd/amdgpu/soc15.c | 18 ++++++++++++++---- + 2 files changed, 20 insertions(+), 8 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +index 5b6f97f4a875..2fa441d9c5a0 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +@@ -1225,11 +1225,13 @@ static int gmc_v9_0_hw_init(void *handle) + gmc_v9_0_init_golden_registers(adev); + + if (adev->mode_info.num_crtc) { +- /* Lockout access through VGA aperture*/ +- WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); ++ if (adev->asic_type != CHIP_ARCTURUS) { ++ /* Lockout access through VGA aperture*/ ++ WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); + +- /* disable VGA render */ +- WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); ++ /* disable VGA render */ ++ WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); ++ } + } + + r = gmc_v9_0_gart_enable(adev); +diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c +index e168d4fa471c..eb87d04cb425 100644 +--- a/drivers/gpu/drm/amd/amdgpu/soc15.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c +@@ -757,14 +757,24 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) + case CHIP_ARCTURUS: + amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); + amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); +- amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); +- if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) +- amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); ++ ++ if (amdgpu_sriov_vf(adev)) { ++ if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) ++ amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); ++ } else { ++ amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); ++ if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) ++ amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); ++ } ++ + if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) + amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); + amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); + amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); +- amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); ++ if (!amdgpu_sriov_vf(adev)) ++ amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); ++ + if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) + amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); + break; +-- +2.17.1 + |