diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3984-drm-amd-powerplay-implement-the-interface-for-settin.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3984-drm-amd-powerplay-implement-the-interface-for-settin.patch | 207 |
1 files changed, 207 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3984-drm-amd-powerplay-implement-the-interface-for-settin.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3984-drm-amd-powerplay-implement-the-interface-for-settin.patch new file mode 100644 index 00000000..e92e4f62 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3984-drm-amd-powerplay-implement-the-interface-for-settin.patch @@ -0,0 +1,207 @@ +From 33ef11ddd78d1e905f2b9566fbc5d90551b8aa56 Mon Sep 17 00:00:00 2001 +From: Prike Liang <Prike.Liang@amd.com> +Date: Tue, 24 Sep 2019 14:40:09 +0800 +Subject: [PATCH 3984/4256] drm/amd/powerplay: implement the interface for + setting soft freq range + +The APU soft freq range set by different way from DGPU, thus need implement +the function respectively base on each common SMU part. + +Signed-off-by: Prike Liang <Prike.Liang@amd.com> +Reviewed-by: Evan Quan <evan.quan@amd.com> +--- + drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 25 +-------- + .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 + + drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 30 ++++++++++ + drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 56 +++++++++++++++++++ + 4 files changed, 91 insertions(+), 23 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +index a307d4a52e87..efc14c7e7bc2 100644 +--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c ++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +@@ -205,8 +205,7 @@ int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t + int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, + uint32_t min, uint32_t max) + { +- int ret = 0, clk_id = 0; +- uint32_t param; ++ int ret = 0; + + if (min <= 0 && max <= 0) + return -EINVAL; +@@ -214,27 +213,7 @@ int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, + if (!smu_clk_dpm_is_enabled(smu, clk_type)) + return 0; + +- clk_id = smu_clk_get_index(smu, clk_type); +- if (clk_id < 0) +- return clk_id; +- +- if (max > 0) { +- param = (uint32_t)((clk_id << 16) | (max & 0xffff)); +- ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq, +- param); +- if (ret) +- return ret; +- } +- +- if (min > 0) { +- param = (uint32_t)((clk_id << 16) | (min & 0xffff)); +- ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq, +- param); +- if (ret) +- return ret; +- } +- +- ++ ret = smu_set_soft_freq_limited_range(smu, clk_type, min, max); + return ret; + } + +diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +index f1b378965551..504d6487c3d2 100644 +--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h ++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +@@ -548,6 +548,7 @@ struct smu_funcs + int (*baco_reset)(struct smu_context *smu); + int (*mode2_reset)(struct smu_context *smu); + int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max); ++ int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max); + }; + + #define smu_init_microcode(smu) \ +@@ -777,6 +778,8 @@ struct smu_funcs + #define smu_get_dpm_uclk_limited(smu, clock, max) \ + ((smu)->ppt_funcs->get_dpm_uclk_limited ? (smu)->ppt_funcs->get_dpm_uclk_limited((smu), (clock), (max)) : -EINVAL) + ++#define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \ ++ ((smu)->funcs->set_soft_freq_limited_range ? (smu)->funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : -EINVAL) + + extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table, + uint16_t *size, uint8_t *frev, uint8_t *crev, +diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c +index 022b5c8672a1..9883f0a4471a 100644 +--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c ++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c +@@ -1762,6 +1762,35 @@ static int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk + return ret; + } + ++static int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, ++ uint32_t min, uint32_t max) ++{ ++ int ret = 0, clk_id = 0; ++ uint32_t param; ++ ++ clk_id = smu_clk_get_index(smu, clk_type); ++ if (clk_id < 0) ++ return clk_id; ++ ++ if (max > 0) { ++ param = (uint32_t)((clk_id << 16) | (max & 0xffff)); ++ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq, ++ param); ++ if (ret) ++ return ret; ++ } ++ ++ if (min > 0) { ++ param = (uint32_t)((clk_id << 16) | (min & 0xffff)); ++ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq, ++ param); ++ if (ret) ++ return ret; ++ } ++ ++ return ret; ++} ++ + static const struct smu_funcs smu_v11_0_funcs = { + .init_microcode = smu_v11_0_init_microcode, + .load_microcode = smu_v11_0_load_microcode, +@@ -1813,6 +1842,7 @@ static const struct smu_funcs smu_v11_0_funcs = { + .baco_set_state = smu_v11_0_baco_set_state, + .baco_reset = smu_v11_0_baco_reset, + .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq, ++ .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range, + }; + + void smu_v11_0_set_smu_funcs(struct smu_context *smu) +diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c +index d9d947375557..d3563f0c44e9 100644 +--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c ++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c +@@ -383,6 +383,61 @@ static int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk + static int smu_v12_0_mode2_reset(struct smu_context *smu){ + return smu_v12_0_send_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_2); + } ++ ++static int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, ++ uint32_t min, uint32_t max) ++{ ++ int ret = 0; ++ ++ if (max < min) ++ return -EINVAL; ++ ++ switch (clk_type) { ++ case SMU_GFXCLK: ++ case SMU_SCLK: ++ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, min); ++ if (ret) ++ return ret; ++ ++ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, max); ++ if (ret) ++ return ret; ++ break; ++ case SMU_FCLK: ++ case SMU_MCLK: ++ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min); ++ if (ret) ++ return ret; ++ ++ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max); ++ if (ret) ++ return ret; ++ break; ++ case SMU_SOCCLK: ++ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min); ++ if (ret) ++ return ret; ++ ++ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max); ++ if (ret) ++ return ret; ++ break; ++ case SMU_VCLK: ++ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinVcn, min); ++ if (ret) ++ return ret; ++ ++ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxVcn, max); ++ if (ret) ++ return ret; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return ret; ++} ++ + static const struct smu_funcs smu_v12_0_funcs = { + .check_fw_status = smu_v12_0_check_fw_status, + .check_fw_version = smu_v12_0_check_fw_version, +@@ -398,6 +453,7 @@ static const struct smu_funcs smu_v12_0_funcs = { + .populate_smc_tables = smu_v12_0_populate_smc_tables, + .get_dpm_ultimate_freq = smu_v12_0_get_dpm_ultimate_freq, + .mode2_reset = smu_v12_0_mode2_reset, ++ .set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range, + }; + + void smu_v12_0_set_smu_funcs(struct smu_context *smu) +-- +2.17.1 + |