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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3920-drm-amdgpu-atomfirmware-simplify-the-interface-to-ge.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3920-drm-amdgpu-atomfirmware-simplify-the-interface-to-ge.patch220
1 files changed, 220 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3920-drm-amdgpu-atomfirmware-simplify-the-interface-to-ge.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3920-drm-amdgpu-atomfirmware-simplify-the-interface-to-ge.patch
new file mode 100644
index 00000000..0df7f70e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3920-drm-amdgpu-atomfirmware-simplify-the-interface-to-ge.patch
@@ -0,0 +1,220 @@
+From 515e4c0ae27fdf3e5066b7261527956f2edf8a5b Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 23 Sep 2019 15:12:46 -0500
+Subject: [PATCH 3920/4256] drm/amdgpu/atomfirmware: simplify the interface to
+ get vram info
+
+fetch both the vram type and width in one function call. This
+avoids having to parse the same data table twice to get the two
+pieces of data.
+
+Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 34 +------------
+ .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h | 4 +-
+ drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 21 +++-----
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 49 ++++++++++---------
+ 4 files changed, 37 insertions(+), 71 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+index e0e67a53fb3c..fbff37bd2b03 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+@@ -169,9 +169,8 @@ static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev,
+ return vram_type;
+ }
+
+-static int
+-amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
+- int *vram_width, int *vram_type)
++int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
++ int *vram_width, int *vram_type)
+ {
+ struct amdgpu_mode_info *mode_info = &adev->mode_info;
+ int index, i = 0;
+@@ -185,7 +184,6 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
+ u32 mem_channel_width;
+ u32 module_id;
+
+-
+ if (adev->flags & AMD_IS_APU)
+ index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+ integratedsysteminfo);
+@@ -261,34 +259,6 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
+ return 0;
+ }
+
+-/*
+- * Return vram width from integrated system info table, if available,
+- * or 0 if not.
+- */
+-int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev)
+-{
+- int vram_width = 0, vram_type = 0;
+- int r = amdgpu_atomfirmware_get_vram_info(adev, &vram_width, &vram_type);
+- if (r)
+- return 0;
+-
+- return vram_width;
+-}
+-
+-/*
+- * Return vram type from either integrated system info table
+- * or umc info table, if available, or 0 (TYPE_UNKNOWN) if not
+- */
+-int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev)
+-{
+- int vram_width = 0, vram_type = 0;
+- int r = amdgpu_atomfirmware_get_vram_info(adev, &vram_width, &vram_type);
+- if (r)
+- return 0;
+-
+- return vram_type;
+-}
+-
+ /*
+ * Return true if vbios enabled ecc by default, if umc info table is available
+ * or false if ecc is not enabled or umc info table is not available
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
+index 5ec6f92f353c..82819f03e444 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
+@@ -29,8 +29,8 @@
+ bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev);
+ void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev);
+ int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev);
+-int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev);
+-int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev);
++int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
++ int *vram_width, int *vram_type);
+ int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev);
+ int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev);
+ bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+index 2ea9278a8368..055a8cbf889b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+@@ -539,17 +539,6 @@ static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,
+ */
+ static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
+ {
+- int chansize, numchan;
+-
+- if (!amdgpu_emu_mode)
+- adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
+- else {
+- /* hard code vram_width for emulation */
+- chansize = 128;
+- numchan = 1;
+- adev->gmc.vram_width = numchan * chansize;
+- }
+-
+ /* Could aper size report 0 ? */
+ adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
+ adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
+@@ -635,8 +624,8 @@ static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev)
+
+ static int gmc_v10_0_sw_init(void *handle)
+ {
+- int r;
+ int dma_bits;
++ int r, vram_width = 0, vram_type = 0;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ gfxhub_v2_0_init(adev);
+@@ -644,7 +633,13 @@ static int gmc_v10_0_sw_init(void *handle)
+
+ spin_lock_init(&adev->gmc.invalidate_lock);
+
+- adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev);
++ r = amdgpu_atomfirmware_get_vram_info(adev, &vram_width, &vram_type);
++ if (!amdgpu_emu_mode)
++ adev->gmc.vram_width = vram_width;
++ else
++ adev->gmc.vram_width = 1 * 128; /* numchan * chansize */
++
++ adev->gmc.vram_type = vram_type;
+ switch (adev->asic_type) {
+ case CHIP_NAVI10:
+ case CHIP_NAVI14:
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 561cc6bef280..abd7a5e22c3f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -891,30 +891,8 @@ static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
+ */
+ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
+ {
+- int chansize, numchan;
+ int r;
+
+- if (amdgpu_sriov_vf(adev)) {
+- /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,
+- * and DF related registers is not readable, seems hardcord is the
+- * only way to set the correct vram_width
+- */
+- adev->gmc.vram_width = 2048;
+- } else if (amdgpu_emu_mode != 1) {
+- adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
+- }
+-
+- if (!adev->gmc.vram_width) {
+- /* hbm memory channel size */
+- if (adev->flags & AMD_IS_APU)
+- chansize = 64;
+- else
+- chansize = 128;
+-
+- numchan = adev->df_funcs->get_hbm_channel_number(adev);
+- adev->gmc.vram_width = numchan * chansize;
+- }
+-
+ /* size in MB on si */
+ adev->gmc.mc_vram_size =
+ adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
+@@ -1029,8 +1007,8 @@ static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
+
+ static int gmc_v9_0_sw_init(void *handle)
+ {
+- int r;
+ int dma_bits;
++ int r, vram_width = 0, vram_type = 0;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ gfxhub_v1_0_init(adev);
+@@ -1041,7 +1019,30 @@ static int gmc_v9_0_sw_init(void *handle)
+
+ spin_lock_init(&adev->gmc.invalidate_lock);
+
+- adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev);
++ r = amdgpu_atomfirmware_get_vram_info(adev, &vram_width, &vram_type);
++ if (amdgpu_sriov_vf(adev))
++ /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,
++ * and DF related registers is not readable, seems hardcord is the
++ * only way to set the correct vram_width
++ */
++ adev->gmc.vram_width = 2048;
++ else if (amdgpu_emu_mode != 1)
++ adev->gmc.vram_width = vram_width;
++
++ if (!adev->gmc.vram_width) {
++ int chansize, numchan;
++
++ /* hbm memory channel size */
++ if (adev->flags & AMD_IS_APU)
++ chansize = 64;
++ else
++ chansize = 128;
++
++ numchan = adev->df_funcs->get_hbm_channel_number(adev);
++ adev->gmc.vram_width = numchan * chansize;
++ }
++
++ adev->gmc.vram_type = vram_type;
+ switch (adev->asic_type) {
+ case CHIP_RAVEN:
+ adev->num_vmhubs = 2;
+--
+2.17.1
+