diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3837-drm-amd-display-Do-not-double-buffer-DTO-adjustments.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3837-drm-amd-display-Do-not-double-buffer-DTO-adjustments.patch | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3837-drm-amd-display-Do-not-double-buffer-DTO-adjustments.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3837-drm-amd-display-Do-not-double-buffer-DTO-adjustments.patch new file mode 100644 index 00000000..e9d69135 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3837-drm-amd-display-Do-not-double-buffer-DTO-adjustments.patch @@ -0,0 +1,58 @@ +From 6f2e055fc0eaeed19b9445543d2bcd7dbda2e7e2 Mon Sep 17 00:00:00 2001 +From: Wesley Chalmers <Wesley.Chalmers@amd.com> +Date: Fri, 23 Aug 2019 10:56:13 -0400 +Subject: [PATCH 3837/4256] drm/amd/display: Do not double-buffer DTO + adjustments + +[WHY] +When changing DPP global ref clock, DTO adjustments must take effect +immediately, or else underflow may occur. +It appears the original decision to double-buffer DTO adjustments was made to +prevent underflows that occur when raising DPP ref clock (which is not +double-buffered), but that same decision causes similar issues when +lowering DPP global ref clock. The better solution is to order the +adjustments according to whether clocks are being raised or lowered. + +Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> +Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Acked-by: Anthony Koo <Anthony.Koo@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +--- + .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c | 21 ------------------- + 1 file changed, 21 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c +index f9b99f8cfc31..313d3793005e 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c +@@ -117,27 +117,6 @@ void dccg2_get_dccg_ref_freq(struct dccg *dccg, + + void dccg2_init(struct dccg *dccg) + { +- struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); +- +- // Fallthrough intentional to program all available dpp_dto's +- switch (dccg_dcn->base.ctx->dc->res_pool->pipe_count) { +- case 6: +- REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[5], 1); +- case 5: +- REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[4], 1); +- case 4: +- REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[3], 1); +- case 3: +- REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[2], 1); +- case 2: +- REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[1], 1); +- case 1: +- REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[0], 1); +- break; +- default: +- ASSERT(false); +- break; +- } + } + + static const struct dccg_funcs dccg2_funcs = { +-- +2.17.1 + |