diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3832-drm-amd-display-add-vtg-update-after-global-sync-upd.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3832-drm-amd-display-add-vtg-update-after-global-sync-upd.patch | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3832-drm-amd-display-add-vtg-update-after-global-sync-upd.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3832-drm-amd-display-add-vtg-update-after-global-sync-upd.patch new file mode 100644 index 00000000..5c114bed --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3832-drm-amd-display-add-vtg-update-after-global-sync-upd.patch @@ -0,0 +1,43 @@ +From 310d024c1aa624538d9fdf7f3c62983792df4e01 Mon Sep 17 00:00:00 2001 +From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Date: Mon, 26 Aug 2019 15:04:18 -0400 +Subject: [PATCH 3832/4256] drm/amd/display: add vtg update after global sync + update + +Global sync update was missing vtg update resulting in underflow if +vstartup decreased a significant amount. + +Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Reviewed-by: Jaehyun Chung <Jaehyun.Chung@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +index faaf8841c61e..4bb5ad19c4cf 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +@@ -1361,7 +1361,7 @@ static void dcn20_program_pipe( + && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe) + dc->hwss.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible); + +- if (pipe_ctx->update_flags.bits.global_sync) ++ if (pipe_ctx->update_flags.bits.global_sync) { + pipe_ctx->stream_res.tg->funcs->program_global_sync( + pipe_ctx->stream_res.tg, + pipe_ctx->pipe_dlg_param.vready_offset, +@@ -1369,6 +1369,10 @@ static void dcn20_program_pipe( + pipe_ctx->pipe_dlg_param.vupdate_offset, + pipe_ctx->pipe_dlg_param.vupdate_width); + ++ pipe_ctx->stream_res.tg->funcs->set_vtg_params( ++ pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); ++ } ++ + if (pipe_ctx->update_flags.bits.odm) + dc->hwss.update_odm(dc, context, pipe_ctx); + +-- +2.17.1 + |