diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3820-drm-amdgpu-cleanup-mtype-mapping.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3820-drm-amdgpu-cleanup-mtype-mapping.patch | 395 |
1 files changed, 395 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3820-drm-amdgpu-cleanup-mtype-mapping.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3820-drm-amdgpu-cleanup-mtype-mapping.patch new file mode 100644 index 00000000..112faf00 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3820-drm-amdgpu-cleanup-mtype-mapping.patch @@ -0,0 +1,395 @@ +From d178e867b2fc43900e5abd09c7c53ac9e3566367 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com> +Date: Mon, 2 Sep 2019 14:52:30 +0200 +Subject: [PATCH 3820/4256] drm/amdgpu: cleanup mtype mapping +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Unify how we map the UAPI flags to the PTE hardware flags for a mapping. + +Only the MTYPE is actually ASIC dependent, all other flags should be +copied over 1 to 1 and ASIC differences are handled later on. + +Signed-off-by: Christian König <christian.koenig@amd.com> +--- + .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +- + drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 32 +++++++++++++- + drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h | 1 + + drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 7 ++-- + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 ++- + drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 40 +++++------------- + drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 16 ------- + drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 16 ------- + drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 18 -------- + drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 42 +++++-------------- + 10 files changed, 59 insertions(+), 121 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +index 92af06fa011a..9ffe63377c99 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +@@ -412,7 +412,7 @@ static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem) + AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC; + } + +- return amdgpu_gmc_get_pte_flags(adev, mapping_flags); ++ return amdgpu_gem_va_map_flags(adev, mapping_flags); + } + + /* add_bo_to_vm - Add a BO to a VM +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +index cbd09e9b1092..59a1e73f4056 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +@@ -617,6 +617,34 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, + DRM_ERROR("Couldn't update BO_VA (%d)\n", r); + } + ++/** ++ * amdgpu_gem_va_map_flags - map GEM UAPI flags into hardware flags ++ * ++ * @adev: amdgpu_device pointer ++ * @flags: GEM UAPI flags ++ * ++ * Returns the GEM UAPI flags mapped into hardware for the ASIC. ++ */ ++uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags) ++{ ++ uint64_t pte_flag = 0; ++ ++ if (flags & AMDGPU_VM_PAGE_EXECUTABLE) ++ pte_flag |= AMDGPU_PTE_EXECUTABLE; ++ if (flags & AMDGPU_VM_PAGE_READABLE) ++ pte_flag |= AMDGPU_PTE_READABLE; ++ if (flags & AMDGPU_VM_PAGE_WRITEABLE) ++ pte_flag |= AMDGPU_PTE_WRITEABLE; ++ if (flags & AMDGPU_VM_PAGE_PRT) ++ pte_flag |= AMDGPU_PTE_PRT; ++ ++ if (adev->gmc.gmc_funcs->map_mtype) ++ pte_flag |= amdgpu_gmc_map_mtype(adev, ++ flags & AMDGPU_VM_MTYPE_MASK); ++ ++ return pte_flag; ++} ++ + int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp) + { +@@ -711,7 +739,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, + + switch (args->operation) { + case AMDGPU_VA_OP_MAP: +- va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags); ++ va_flags = amdgpu_gem_va_map_flags(adev, args->flags); + r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, + args->offset_in_bo, args->map_size, + va_flags); +@@ -726,7 +754,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, + args->map_size); + break; + case AMDGPU_VA_OP_REPLACE: +- va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags); ++ va_flags = amdgpu_gem_va_map_flags(adev, args->flags); + r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address, + args->offset_in_bo, args->map_size, + va_flags); +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h +index 206c5fa2c18f..ff7f8de62655 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h +@@ -69,6 +69,7 @@ int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp); + int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp); ++uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags); + int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp); + int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +index df012766d907..a669c5826415 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +@@ -99,9 +99,8 @@ struct amdgpu_gmc_funcs { + unsigned pasid); + /* enable/disable PRT support */ + void (*set_prt)(struct amdgpu_device *adev, bool enable); +- /* set pte flags based per asic */ +- uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev, +- uint32_t flags); ++ /* map mtype to hardware flags */ ++ uint64_t (*map_mtype)(struct amdgpu_device *adev, uint32_t flags); + /* get the pde for a given mc addr */ + void (*get_vm_pde)(struct amdgpu_device *adev, int level, + u64 *dst, u64 *flags); +@@ -185,8 +184,8 @@ struct amdgpu_gmc { + #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type))) + #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr)) + #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid)) ++#define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags)) + #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags)) +-#define amdgpu_gmc_get_pte_flags(adev, flags) (adev)->gmc.gmc_funcs->get_vm_pte_flags((adev),(flags)) + + /** + * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +index db1fe417fc95..d85753632840 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +@@ -1585,8 +1585,10 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, + if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) + flags &= ~AMDGPU_PTE_WRITEABLE; + +- flags &= ~AMDGPU_PTE_EXECUTABLE; +- flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; ++ if (adev->asic_type >= CHIP_TONGA) { ++ flags &= ~AMDGPU_PTE_EXECUTABLE; ++ flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; ++ } + + if (adev->asic_type >= CHIP_NAVI10) { + flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +index 2f9f881b810d..ebc2abbbf039 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +@@ -397,43 +397,23 @@ static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid + * 1 system + * 0 valid + */ +-static uint64_t gmc_v10_0_get_vm_pte_flags(struct amdgpu_device *adev, +- uint32_t flags) +-{ +- uint64_t pte_flag = 0; +- +- if (flags & AMDGPU_VM_PAGE_EXECUTABLE) +- pte_flag |= AMDGPU_PTE_EXECUTABLE; +- if (flags & AMDGPU_VM_PAGE_READABLE) +- pte_flag |= AMDGPU_PTE_READABLE; +- if (flags & AMDGPU_VM_PAGE_WRITEABLE) +- pte_flag |= AMDGPU_PTE_WRITEABLE; + +- switch (flags & AMDGPU_VM_MTYPE_MASK) { ++static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) ++{ ++ switch (flags) { + case AMDGPU_VM_MTYPE_DEFAULT: +- pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); +- break; ++ return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); + case AMDGPU_VM_MTYPE_NC: +- pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); +- break; ++ return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); + case AMDGPU_VM_MTYPE_WC: +- pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); +- break; ++ return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); + case AMDGPU_VM_MTYPE_CC: +- pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); +- break; ++ return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); + case AMDGPU_VM_MTYPE_UC: +- pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); +- break; ++ return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); + default: +- pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); +- break; ++ return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); + } +- +- if (flags & AMDGPU_VM_PAGE_PRT) +- pte_flag |= AMDGPU_PTE_PRT; +- +- return pte_flag; + } + + static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level, +@@ -464,7 +444,7 @@ static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = { + .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb, + .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb, + .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping, +- .get_vm_pte_flags = gmc_v10_0_get_vm_pte_flags, ++ .map_mtype = gmc_v10_0_map_mtype, + .get_vm_pde = gmc_v10_0_get_vm_pde + }; + +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +index e60b6a5f170a..2b6a0d27f085 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +@@ -383,21 +383,6 @@ static uint64_t gmc_v6_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, + return pd_addr; + } + +-static uint64_t gmc_v6_0_get_vm_pte_flags(struct amdgpu_device *adev, +- uint32_t flags) +-{ +- uint64_t pte_flag = 0; +- +- if (flags & AMDGPU_VM_PAGE_READABLE) +- pte_flag |= AMDGPU_PTE_READABLE; +- if (flags & AMDGPU_VM_PAGE_WRITEABLE) +- pte_flag |= AMDGPU_PTE_WRITEABLE; +- if (flags & AMDGPU_VM_PAGE_PRT) +- pte_flag |= AMDGPU_PTE_PRT; +- +- return pte_flag; +-} +- + static void gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, int level, + uint64_t *addr, uint64_t *flags) + { +@@ -1159,7 +1144,6 @@ static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = { + .emit_flush_gpu_tlb = gmc_v6_0_emit_flush_gpu_tlb, + .set_prt = gmc_v6_0_set_prt, + .get_vm_pde = gmc_v6_0_get_vm_pde, +- .get_vm_pte_flags = gmc_v6_0_get_vm_pte_flags + }; + + static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = { +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +index ef628f7b2a0e..5a47f5c4a118 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +@@ -460,21 +460,6 @@ static void gmc_v7_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, + amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); + } + +-static uint64_t gmc_v7_0_get_vm_pte_flags(struct amdgpu_device *adev, +- uint32_t flags) +-{ +- uint64_t pte_flag = 0; +- +- if (flags & AMDGPU_VM_PAGE_READABLE) +- pte_flag |= AMDGPU_PTE_READABLE; +- if (flags & AMDGPU_VM_PAGE_WRITEABLE) +- pte_flag |= AMDGPU_PTE_WRITEABLE; +- if (flags & AMDGPU_VM_PAGE_PRT) +- pte_flag |= AMDGPU_PTE_PRT; +- +- return pte_flag; +-} +- + static void gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, int level, + uint64_t *addr, uint64_t *flags) + { +@@ -1355,7 +1340,6 @@ static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = { + .emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb, + .emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping, + .set_prt = gmc_v7_0_set_prt, +- .get_vm_pte_flags = gmc_v7_0_get_vm_pte_flags, + .get_vm_pde = gmc_v7_0_get_vm_pde + }; + +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +index d42610450807..8519d1346a37 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +@@ -688,23 +688,6 @@ static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, + * 0 valid + */ + +-static uint64_t gmc_v8_0_get_vm_pte_flags(struct amdgpu_device *adev, +- uint32_t flags) +-{ +- uint64_t pte_flag = 0; +- +- if (flags & AMDGPU_VM_PAGE_EXECUTABLE) +- pte_flag |= AMDGPU_PTE_EXECUTABLE; +- if (flags & AMDGPU_VM_PAGE_READABLE) +- pte_flag |= AMDGPU_PTE_READABLE; +- if (flags & AMDGPU_VM_PAGE_WRITEABLE) +- pte_flag |= AMDGPU_PTE_WRITEABLE; +- if (flags & AMDGPU_VM_PAGE_PRT) +- pte_flag |= AMDGPU_PTE_PRT; +- +- return pte_flag; +-} +- + static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level, + uint64_t *addr, uint64_t *flags) + { +@@ -1728,7 +1711,6 @@ static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = { + .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb, + .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping, + .set_prt = gmc_v8_0_set_prt, +- .get_vm_pte_flags = gmc_v8_0_get_vm_pte_flags, + .get_vm_pde = gmc_v8_0_get_vm_pde + }; + +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +index fe63f64c4db3..c95e62023e5e 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +@@ -609,47 +609,25 @@ static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, + * 0 valid + */ + +-static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev, +- uint32_t flags) ++static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) + + { +- uint64_t pte_flag = 0; +- +- if (flags & AMDGPU_VM_PAGE_EXECUTABLE) +- pte_flag |= AMDGPU_PTE_EXECUTABLE; +- if (flags & AMDGPU_VM_PAGE_READABLE) +- pte_flag |= AMDGPU_PTE_READABLE; +- if (flags & AMDGPU_VM_PAGE_WRITEABLE) +- pte_flag |= AMDGPU_PTE_WRITEABLE; +- +- switch (flags & AMDGPU_VM_MTYPE_MASK) { ++ switch (flags) { + case AMDGPU_VM_MTYPE_DEFAULT: +- pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); +- break; ++ return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); + case AMDGPU_VM_MTYPE_NC: +- pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); +- break; ++ return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); + case AMDGPU_VM_MTYPE_WC: +- pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_WC); +- break; ++ return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC); + case AMDGPU_VM_MTYPE_RW: +- pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_RW); +- break; ++ return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW); + case AMDGPU_VM_MTYPE_CC: +- pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_CC); +- break; ++ return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC); + case AMDGPU_VM_MTYPE_UC: +- pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_UC); +- break; ++ return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC); + default: +- pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); +- break; ++ return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); + } +- +- if (flags & AMDGPU_VM_PAGE_PRT) +- pte_flag |= AMDGPU_PTE_PRT; +- +- return pte_flag; + } + + static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, +@@ -680,7 +658,7 @@ static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { + .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, + .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, + .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, +- .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags, ++ .map_mtype = gmc_v9_0_map_mtype, + .get_vm_pde = gmc_v9_0_get_vm_pde + }; + +-- +2.17.1 + |