diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3796-drm-amdgpu-allow-direct-submission-of-PTE-updates.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3796-drm-amdgpu-allow-direct-submission-of-PTE-updates.patch | 86 |
1 files changed, 86 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3796-drm-amdgpu-allow-direct-submission-of-PTE-updates.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3796-drm-amdgpu-allow-direct-submission-of-PTE-updates.patch new file mode 100644 index 00000000..a788b732 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3796-drm-amdgpu-allow-direct-submission-of-PTE-updates.patch @@ -0,0 +1,86 @@ +From 9ba9bc43fa7d25e1127aa7be0afb3b404b4025c1 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com> +Date: Wed, 27 Mar 2019 13:59:23 +0100 +Subject: [PATCH 3796/4256] drm/amdgpu: allow direct submission of PTE updates +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +For handling PTE updates directly in the fault handler. + +Signed-off-by: Christian König <christian.koenig@amd.com> +Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 18 ++++++++++-------- + 1 file changed, 10 insertions(+), 8 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +index c787f71ef6a0..364a17683506 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +@@ -1457,13 +1457,14 @@ static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params, + * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table + * + * @adev: amdgpu_device pointer +- * @exclusive: fence we need to sync to +- * @pages_addr: DMA addresses to use for mapping + * @vm: requested vm ++ * @direct: direct submission in a page fault ++ * @exclusive: fence we need to sync to + * @start: start of mapped range + * @last: last mapped entry + * @flags: flags for the entries + * @addr: addr to set the area to ++ * @pages_addr: DMA addresses to use for mapping + * @fence: optional resulting fence + * + * Fill in the page table entries between @start and @last. +@@ -1472,11 +1473,11 @@ static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params, + * 0 for success, -EINVAL for failure. + */ + static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, ++ struct amdgpu_vm *vm, bool direct, + struct dma_fence *exclusive, +- dma_addr_t *pages_addr, +- struct amdgpu_vm *vm, + uint64_t start, uint64_t last, + uint64_t flags, uint64_t addr, ++ dma_addr_t *pages_addr, + struct dma_fence **fence) + { + struct amdgpu_vm_update_params params; +@@ -1486,6 +1487,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, + memset(¶ms, 0, sizeof(params)); + params.adev = adev; + params.vm = vm; ++ params.direct = direct; + params.pages_addr = pages_addr; + + /* sync to everything on unmapping */ +@@ -1617,9 +1619,9 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, + } + + last = min((uint64_t)mapping->last, start + max_entries - 1); +- r = amdgpu_vm_bo_update_mapping(adev, exclusive, dma_addr, vm, ++ r = amdgpu_vm_bo_update_mapping(adev, vm, false, exclusive, + start, last, flags, addr, +- fence); ++ dma_addr, fence); + if (r) + return r; + +@@ -1913,9 +1915,9 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev, + mapping->start < AMDGPU_GMC_HOLE_START) + init_pte_value = AMDGPU_PTE_DEFAULT_ATC; + +- r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm, ++ r = amdgpu_vm_bo_update_mapping(adev, vm, false, NULL, + mapping->start, mapping->last, +- init_pte_value, 0, &f); ++ init_pte_value, 0, NULL, &f); + amdgpu_vm_free_mapping(adev, vm, mapping, f); + if (r) { + dma_fence_put(f); +-- +2.17.1 + |