diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3784-drm-amd-powerplay-properly-set-mp1-state-for-SW-SMU-.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3784-drm-amd-powerplay-properly-set-mp1-state-for-SW-SMU-.patch | 110 |
1 files changed, 110 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3784-drm-amd-powerplay-properly-set-mp1-state-for-SW-SMU-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3784-drm-amd-powerplay-properly-set-mp1-state-for-SW-SMU-.patch new file mode 100644 index 00000000..869e0f0a --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3784-drm-amd-powerplay-properly-set-mp1-state-for-SW-SMU-.patch @@ -0,0 +1,110 @@ +From 9cf8bd1e00f9533c2af5c980d9a157d1dae5f853 Mon Sep 17 00:00:00 2001 +From: Evan Quan <evan.quan@amd.com> +Date: Wed, 11 Sep 2019 19:35:45 +0800 +Subject: [PATCH 3784/4256] drm/amd/powerplay: properly set mp1 state for SW + SMU suspend/reset routine + +Set mp1 state properly for SW SMU suspend/reset routine. + +Change-Id: I458d09e79bba2613bb85099938648782ff91b97a +Signed-off-by: Evan Quan <evan.quan@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 11 ++--- + drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 40 +++++++++++++++++++ + .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 2 + + 3 files changed, 48 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +index 8d113a29b0df..078df285b86a 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -2221,16 +2221,17 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) + /* handle putting the SMC in the appropriate state */ + if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { + if (is_support_sw_smu(adev)) { +- /* todo */ ++ r = smu_set_mp1_state(&adev->smu, adev->mp1_state); + } else if (adev->powerplay.pp_funcs && + adev->powerplay.pp_funcs->set_mp1_state) { + r = adev->powerplay.pp_funcs->set_mp1_state( + adev->powerplay.pp_handle, + adev->mp1_state); +- if (r) { +- DRM_ERROR("SMC failed to set mp1 state %d, %d\n", +- adev->mp1_state, r); +- } ++ } ++ if (r) { ++ DRM_ERROR("SMC failed to set mp1 state %d, %d\n", ++ adev->mp1_state, r); ++ return r; + } + } + +diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +index e18bfce25dfa..a10387f51e21 100644 +--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c ++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +@@ -1788,6 +1788,46 @@ int smu_force_clk_levels(struct smu_context *smu, + return ret; + } + ++int smu_set_mp1_state(struct smu_context *smu, ++ enum pp_mp1_state mp1_state) ++{ ++ uint16_t msg; ++ int ret; ++ ++ /* ++ * The SMC is not fully ready. That may be ++ * expected as the IP may be masked. ++ * So, just return without error. ++ */ ++ if (!smu->pm_enabled) ++ return 0; ++ ++ switch (mp1_state) { ++ case PP_MP1_STATE_SHUTDOWN: ++ msg = SMU_MSG_PrepareMp1ForShutdown; ++ break; ++ case PP_MP1_STATE_UNLOAD: ++ msg = SMU_MSG_PrepareMp1ForUnload; ++ break; ++ case PP_MP1_STATE_RESET: ++ msg = SMU_MSG_PrepareMp1ForReset; ++ break; ++ case PP_MP1_STATE_NONE: ++ default: ++ return 0; ++ } ++ ++ /* some asics may not support those messages */ ++ if (smu_msg_get_index(smu, msg) < 0) ++ return 0; ++ ++ ret = smu_send_smc_msg(smu, msg); ++ if (ret) ++ pr_err("[PrepareMp1] Failed!\n"); ++ ++ return ret; ++} ++ + const struct amd_ip_funcs smu_ip_funcs = { + .name = "smu", + .early_init = smu_early_init, +diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +index 88f1ee9a2f1d..45da21dc2356 100644 +--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h ++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +@@ -836,5 +836,7 @@ int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask); + int smu_force_clk_levels(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t mask); ++int smu_set_mp1_state(struct smu_context *smu, ++ enum pp_mp1_state mp1_state); + + #endif +-- +2.17.1 + |