diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3777-drm-amdgpu-implement-ras-query-function-for-pcie-bif.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3777-drm-amdgpu-implement-ras-query-function-for-pcie-bif.patch | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3777-drm-amdgpu-implement-ras-query-function-for-pcie-bif.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3777-drm-amdgpu-implement-ras-query-function-for-pcie-bif.patch new file mode 100644 index 00000000..5d386e7e --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3777-drm-amdgpu-implement-ras-query-function-for-pcie-bif.patch @@ -0,0 +1,60 @@ +From 250281209ac40233db6c61c2a96acb30081dd668 Mon Sep 17 00:00:00 2001 +From: Guchun Chen <guchun.chen@amd.com> +Date: Wed, 11 Sep 2019 11:12:17 +0800 +Subject: [PATCH 3777/4256] drm/amdgpu: implement ras query function for pcie + bif + +ras error query funtionality implementation + +Change-Id: Id7d8c35621960685a2a7507e4e95939f5a05bdc6 +Signed-off-by: Tao Zhou <tao.zhou1@amd.com> +Signed-off-by: Guchun Chen <guchun.chen@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 30 ++++++++++++++++++++++++++ + 1 file changed, 30 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c +index fa6a8918dc8c..b776332d979f 100644 +--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c ++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c +@@ -476,6 +476,36 @@ static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *a + static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev, + void *ras_error_status) + { ++ uint32_t global_sts, central_sts, int_eoi; ++ uint32_t corr, fatal, non_fatal; ++ struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; ++ ++ global_sts = RREG32_PCIE(smnRAS_GLOBAL_STATUS_LO); ++ corr = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrCorr); ++ fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrFatal); ++ non_fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ++ ParityErrNonFatal); ++ ++ if (corr) ++ err_data->ce_count++; ++ if (fatal) ++ err_data->ue_count++; ++ ++ if (corr || fatal || non_fatal) { ++ central_sts = RREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS); ++ /* clear error status register */ ++ WREG32_PCIE(smnRAS_GLOBAL_STATUS_LO, global_sts); ++ ++ if (REG_GET_FIELD(central_sts, BIFL_RAS_CENTRAL_STATUS, ++ BIFL_RasContller_Intr_Recv)) { ++ /* clear interrupt status register */ ++ WREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS, central_sts); ++ int_eoi = RREG32_PCIE(smnIOHC_INTERRUPT_EOI); ++ int_eoi = REG_SET_FIELD(int_eoi, ++ IOHC_INTERRUPT_EOI, SMI_EOI, 1); ++ WREG32_PCIE(smnIOHC_INTERRUPT_EOI, int_eoi); ++ } ++ } + } + + const struct amdgpu_nbio_funcs nbio_v7_4_funcs = { +-- +2.17.1 + |