diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3776-drm-amdgpu-add-pcie-bif-ras-related-registers.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3776-drm-amdgpu-add-pcie-bif-ras-related-registers.patch | 99 |
1 files changed, 99 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3776-drm-amdgpu-add-pcie-bif-ras-related-registers.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3776-drm-amdgpu-add-pcie-bif-ras-related-registers.patch new file mode 100644 index 00000000..8f37cc1e --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3776-drm-amdgpu-add-pcie-bif-ras-related-registers.patch @@ -0,0 +1,99 @@ +From 1b7282c7d20b1437344b29cfe60b7a5cfb504876 Mon Sep 17 00:00:00 2001 +From: Guchun Chen <guchun.chen@amd.com> +Date: Wed, 11 Sep 2019 11:10:02 +0800 +Subject: [PATCH 3776/4256] drm/amdgpu: add pcie bif ras related registers + +These registers will be accessed for querying ras errors. + +Change-Id: If263879c43b2a5a6136a2fb04990daddd860567d +Signed-off-by: Tao Zhou <tao.zhou1@amd.com> +Signed-off-by: Guchun Chen <guchun.chen@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +--- + .../include/asic_reg/nbio/nbio_7_4_0_smn.h | 12 ++++++ + .../include/asic_reg/nbio/nbio_7_4_sh_mask.h | 43 +++++++++++++++++++ + 2 files changed, 55 insertions(+) + +diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h +index 4bcacf529852..991128bb9476 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h +@@ -22,6 +22,9 @@ + #ifndef _nbio_7_4_0_SMN_HEADER + #define _nbio_7_4_0_SMN_HEADER + ++// addressBlock: nbio_nbif0_bif_ras_bif_ras_regblk ++// base address: 0x10100000 ++#define smnBIFL_RAS_CENTRAL_STATUS 0x10139040 + + #define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c + #define smnCPM_CONTROL 0x11180460 +@@ -53,4 +56,13 @@ + #define smnPCIE_RX_NUM_NAK 0x11180038 + #define smnPCIE_RX_NUM_NAK_GENERATED 0x1118003c + ++// addressBlock: nbio_iohub_nb_misc_misc_cfgdec ++// base address: 0x13a10000 ++#define smnIOHC_INTERRUPT_EOI 0x13a10120 ++ ++// addressBlock: nbio_iohub_nb_rascfg_ras_cfgdec ++// base address: 0x13a20000 ++#define smnRAS_GLOBAL_STATUS_LO 0x13a20020 ++#define smnRAS_GLOBAL_STATUS_HI 0x13a20024 ++ + #endif // _nbio_7_4_0_SMN_HEADER +diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h +index f9829f577364..07f04b2b5bdd 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h +@@ -48436,4 +48436,47 @@ + #define RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + #define RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L + ++//IOHC_INTERRUPT_EOI ++#define IOHC_INTERRUPT_EOI__SMI_EOI__SHIFT 0x0 ++#define IOHC_INTERRUPT_EOI__SCI_EOI__SHIFT 0x1 ++#define IOHC_INTERRUPT_EOI__NMI_EOI__SHIFT 0x2 ++#define IOHC_INTERRUPT_EOI__SMI_EOI_MASK 0x00000001L ++#define IOHC_INTERRUPT_EOI__SCI_EOI_MASK 0x00000002L ++#define IOHC_INTERRUPT_EOI__NMI_EOI_MASK 0x00000004L ++ ++//RAS_GLOBAL_STATUS_LO ++#define RAS_GLOBAL_STATUS_LO__ParityErrCorr__SHIFT 0x0 ++#define RAS_GLOBAL_STATUS_LO__ParityErrNonFatal__SHIFT 0x1 ++#define RAS_GLOBAL_STATUS_LO__ParityErrFatal__SHIFT 0x2 ++#define RAS_GLOBAL_STATUS_LO__ParityErrSerr__SHIFT 0x3 ++#define RAS_GLOBAL_STATUS_LO__HPLGWA_NMI__SHIFT 0x6 ++#define RAS_GLOBAL_STATUS_LO__HPLGWA_SCI__SHIFT 0x7 ++#define RAS_GLOBAL_STATUS_LO__HPLGWA_SMI__SHIFT 0x8 ++#define RAS_GLOBAL_STATUS_LO__SW_SMI__SHIFT 0x9 ++#define RAS_GLOBAL_STATUS_LO__SW_SCI__SHIFT 0xa ++#define RAS_GLOBAL_STATUS_LO__SW_NMI__SHIFT 0xb ++#define RAS_GLOBAL_STATUS_LO__APML_NMI__SHIFT 0xc ++#define RAS_GLOBAL_STATUS_LO__APML_SyncFld__SHIFT 0xd ++#define RAS_GLOBAL_STATUS_LO__PIN_SyncFld_NMI__SHIFT 0xe ++#define RAS_GLOBAL_STATUS_LO__APML_SyncFld_Private__SHIFT 0xf ++#define RAS_GLOBAL_STATUS_LO__ParityErrCorr_MASK 0x00000001L ++#define RAS_GLOBAL_STATUS_LO__ParityErrNonFatal_MASK 0x00000002L ++#define RAS_GLOBAL_STATUS_LO__ParityErrFatal_MASK 0x00000004L ++#define RAS_GLOBAL_STATUS_LO__ParityErrSerr_MASK 0x00000008L ++#define RAS_GLOBAL_STATUS_LO__HPLGWA_NMI_MASK 0x00000040L ++#define RAS_GLOBAL_STATUS_LO__HPLGWA_SCI_MASK 0x00000080L ++#define RAS_GLOBAL_STATUS_LO__HPLGWA_SMI_MASK 0x00000100L ++#define RAS_GLOBAL_STATUS_LO__SW_SMI_MASK 0x00000200L ++#define RAS_GLOBAL_STATUS_LO__SW_SCI_MASK 0x00000400L ++#define RAS_GLOBAL_STATUS_LO__SW_NMI_MASK 0x00000800L ++#define RAS_GLOBAL_STATUS_LO__APML_NMI_MASK 0x00001000L ++#define RAS_GLOBAL_STATUS_LO__APML_SyncFld_MASK 0x00002000L ++#define RAS_GLOBAL_STATUS_LO__PIN_SyncFld_NMI_MASK 0x00004000L ++#define RAS_GLOBAL_STATUS_LO__APML_SyncFld_Private_MASK 0x00008000L ++//RAS_GLOBAL_STATUS_HI ++#define RAS_GLOBAL_STATUS_HI__PCIE0PortAErr__SHIFT 0x0 ++#define RAS_GLOBAL_STATUS_HI__NBIF0PortAErr__SHIFT 0x1 ++#define RAS_GLOBAL_STATUS_HI__PCIE0PortAErr_MASK 0x00000001L ++#define RAS_GLOBAL_STATUS_HI__NBIF0PortAErr_MASK 0x00000002L ++ + #endif +-- +2.17.1 + |