diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3741-drm-amdgpu-gmc-switch-to-amdgpu_gmc_ras_late_init-he.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3741-drm-amdgpu-gmc-switch-to-amdgpu_gmc_ras_late_init-he.patch | 156 |
1 files changed, 156 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3741-drm-amdgpu-gmc-switch-to-amdgpu_gmc_ras_late_init-he.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3741-drm-amdgpu-gmc-switch-to-amdgpu_gmc_ras_late_init-he.patch new file mode 100644 index 00000000..02fb761e --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3741-drm-amdgpu-gmc-switch-to-amdgpu_gmc_ras_late_init-he.patch @@ -0,0 +1,156 @@ +From da203b1ef5606035e1d0ef74c91a1da68cb30806 Mon Sep 17 00:00:00 2001 +From: Hawking Zhang <Hawking.Zhang@amd.com> +Date: Tue, 3 Sep 2019 05:24:35 +0800 +Subject: [PATCH 3741/4256] drm/amdgpu/gmc: switch to amdgpu_gmc_ras_late_init + helper function + +amdgpu_gmc_ras_late_init is used to init gmc specfic +ras debugfs/sysfs node and gmc specific interrupt handler. +It can be shared among gmc generations. + +Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> +Reviewed-by: Tao Zhou <tao.zhou1@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 49 +++++++++++++++++++++++++ + drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 2 + + drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 36 +----------------- + 3 files changed, 53 insertions(+), 34 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +index 6094990dcbee..51890b1d8522 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +@@ -25,6 +25,7 @@ + */ + + #include "amdgpu.h" ++#include "amdgpu_ras.h" + + /** + * amdgpu_gmc_get_pde_for_bo - get the PDE for a BO +@@ -303,3 +304,51 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr, + gmc->fault_hash[hash].idx = gmc->last_fault++; + return false; + } ++ ++int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev, ++ void *ras_ih_info) ++{ ++ int r; ++ struct ras_ih_if *ih_info = (struct ras_ih_if *)ras_ih_info; ++ struct ras_fs_if fs_info = { ++ .sysfs_name = "umc_err_count", ++ .debugfs_name = "umc_err_inject", ++ }; ++ ++ if (!ih_info) ++ return -EINVAL; ++ ++ if (!adev->gmc.umc_ras_if) { ++ adev->gmc.umc_ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL); ++ if (!adev->gmc.umc_ras_if) ++ return -ENOMEM; ++ adev->gmc.umc_ras_if->block = AMDGPU_RAS_BLOCK__UMC; ++ adev->gmc.umc_ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; ++ adev->gmc.umc_ras_if->sub_block_index = 0; ++ strcpy(adev->gmc.umc_ras_if->name, "umc"); ++ } ++ ih_info->head = fs_info.head = *adev->gmc.umc_ras_if; ++ ++ r = amdgpu_ras_late_init(adev, adev->gmc.umc_ras_if, ++ &fs_info, ih_info); ++ if (r) ++ goto free; ++ ++ if (amdgpu_ras_is_supported(adev, adev->gmc.umc_ras_if->block)) { ++ r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0); ++ if (r) ++ goto late_fini; ++ } else { ++ r = 0; ++ goto free; ++ } ++ ++ return 0; ++ ++late_fini: ++ amdgpu_ras_late_fini(adev, adev->gmc.umc_ras_if, ih_info); ++free: ++ kfree(adev->gmc.umc_ras_if); ++ adev->gmc.umc_ras_if = NULL; ++ return r; ++} +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +index e03351f0ba5a..03687fa01817 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +@@ -230,5 +230,7 @@ void amdgpu_gmc_agp_location(struct amdgpu_device *adev, + struct amdgpu_gmc *mc); + bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr, + uint16_t pasid, uint64_t timestamp); ++int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev, ++ void *ih_info); + + #endif +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +index a72c63124d50..d5c18deb407a 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +@@ -767,39 +767,13 @@ static int gmc_v9_0_ecc_late_init(void *handle) + { + int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; +- struct ras_fs_if umc_fs_info = { +- .sysfs_name = "umc_err_count", +- .debugfs_name = "umc_err_inject", +- }; + struct ras_ih_if umc_ih_info = { + .cb = gmc_v9_0_process_ras_data_cb, + }; + +- if (!adev->gmc.umc_ras_if) { +- adev->gmc.umc_ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL); +- if (!adev->gmc.umc_ras_if) +- return -ENOMEM; +- adev->gmc.umc_ras_if->block = AMDGPU_RAS_BLOCK__UMC; +- adev->gmc.umc_ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; +- adev->gmc.umc_ras_if->sub_block_index = 0; +- strcpy(adev->gmc.umc_ras_if->name, "umc"); +- } +- umc_ih_info.head = umc_fs_info.head = *adev->gmc.umc_ras_if; +- +- r = amdgpu_ras_late_init(adev, adev->gmc.umc_ras_if, +- &umc_fs_info, &umc_ih_info); ++ r = amdgpu_gmc_ras_late_init(adev, &umc_ih_info); + if (r) +- goto free; +- +- if (amdgpu_ras_is_supported(adev, adev->gmc.umc_ras_if->block)) { +- r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0); +- if (r) +- goto umc_late_fini; +- } else { +- /* free umc ras_if if umc ras is not supported */ +- r = 0; +- goto free; +- } ++ return r; + + if (adev->mmhub_funcs && adev->mmhub_funcs->ras_late_init) { + r = adev->mmhub_funcs->ras_late_init(adev); +@@ -807,12 +781,6 @@ static int gmc_v9_0_ecc_late_init(void *handle) + return r; + } + return 0; +-umc_late_fini: +- amdgpu_ras_late_fini(adev, adev->gmc.umc_ras_if, &umc_ih_info); +-free: +- kfree(adev->gmc.umc_ras_if); +- adev->gmc.umc_ras_if = NULL; +- return r; + } + + static int gmc_v9_0_late_init(void *handle) +-- +2.17.1 + |