diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3723-drm-amdgpu-Add-a-kernel-parameter-for-specifying-the.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3723-drm-amdgpu-Add-a-kernel-parameter-for-specifying-the.patch | 283 |
1 files changed, 283 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3723-drm-amdgpu-Add-a-kernel-parameter-for-specifying-the.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3723-drm-amdgpu-Add-a-kernel-parameter-for-specifying-the.patch new file mode 100644 index 00000000..ae36effa --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3723-drm-amdgpu-Add-a-kernel-parameter-for-specifying-the.patch @@ -0,0 +1,283 @@ +From a72d05380ab34f16462a14fbf7a695ea410b5f77 Mon Sep 17 00:00:00 2001 +From: Yong Zhao <Yong.Zhao@amd.com> +Date: Fri, 30 Aug 2019 18:09:10 -0400 +Subject: [PATCH 3723/4256] drm/amdgpu: Add a kernel parameter for specifying + the asic type + +As more and more new asics start to reuse the old device IDs before +launch, there is a need to quickly override the existing asic type +corresponding to the reused device ID through a kernel parameter. With +this, engineers no longer need to rely on local hack patches, +facilitating cooperation across teams. + +Change-Id: Ic948ec8125bf28c9775f2f27673d0b69f2916c71 +Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 ++- + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 11 ++++ + drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 - + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 +- + drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 3 - + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 - + drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 1 - + .../drm/amd/powerplay/hwmgr/processpptables.c | 8 +-- + include/drm/amd_asic_type.h | 55 +++++++++---------- + 10 files changed, 51 insertions(+), 43 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +index 125987f884a9..b2999b81f923 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +@@ -172,6 +172,7 @@ extern int amdgpu_mcbp; + extern int amdgpu_discovery; + extern int amdgpu_mes; + extern int amdgpu_noretry; ++extern int amdgpu_force_asic_type; + + #ifdef CONFIG_DRM_AMDGPU_SI + extern int amdgpu_si_support; +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +index b7276f9e814b..2d65e8eb687d 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -2489,7 +2489,6 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) + case CHIP_VEGA20: + #if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case CHIP_RAVEN: +- case CHIP_PICASSO: + #endif + #if defined(CONFIG_DRM_AMD_DC_DCN2_0) + case CHIP_NAVI10: +@@ -2560,7 +2559,12 @@ int amdgpu_device_init(struct amdgpu_device *adev, + adev->ddev = ddev; + adev->pdev = pdev; + adev->flags = flags; +- adev->asic_type = flags & AMD_ASIC_MASK; ++ ++ if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST) ++ adev->asic_type = amdgpu_force_asic_type; ++ else ++ adev->asic_type = flags & AMD_ASIC_MASK; ++ + adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; + if (amdgpu_emu_mode == 1) + adev->usec_timeout *= 2; +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +index 23fce40922e9..2de8db5e864c 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +@@ -147,6 +147,7 @@ int amdgpu_mcbp = 0; + int amdgpu_discovery = -1; + int amdgpu_mes = 0; + int amdgpu_noretry = 1; ++int amdgpu_force_asic_type = -1; + + struct amdgpu_mgpu_info mgpu_info = { + .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), +@@ -626,6 +627,16 @@ MODULE_PARM_DESC(noretry, + "Disable retry faults (0 = retry enabled, 1 = retry disabled (default))"); + module_param_named(noretry, amdgpu_noretry, int, 0644); + ++/** ++ * DOC: force_asic_type (int) ++ * A non negative value used to specify the asic type for all supported GPUs. ++ */ ++MODULE_PARM_DESC(force_asic_type, ++ "A non negative value used to specify the asic type for all supported GPUs"); ++module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); ++ ++ ++ + #ifdef CONFIG_HSA_AMD + /** + * DOC: sched_policy (int) +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +index d92444ac1fc5..52b02ce626e1 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +@@ -50,7 +50,6 @@ static int psp_early_init(void *handle) + psp->autoload_supported = false; + break; + case CHIP_RAVEN: +- case CHIP_PICASSO: + psp_v10_0_set_psp_funcs(psp); + psp->autoload_supported = false; + break; +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +index dd5b5875f874..31b25d27e50e 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +@@ -2660,7 +2660,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, + vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & + AMDGPU_VM_USE_CPU_FOR_COMPUTE); + +- if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_PICASSO) ++ if (adev->asic_type == CHIP_RAVEN) + vm->pte_support_ats = true; + } else { + vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & +@@ -2785,7 +2785,7 @@ static int amdgpu_vm_check_clean_reserved(struct amdgpu_device *adev, + */ + int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm) + { +- bool pte_support_ats = (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_PICASSO); ++ bool pte_support_ats = (adev->asic_type == CHIP_RAVEN); + int r; + + r = amdgpu_bo_reserve(vm->root.base.bo, true); +diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c +index 216af0af255a..e5fff6b30137 100644 +--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c +@@ -57,9 +57,6 @@ static int psp_v10_0_init_microcode(struct psp_context *psp) + else + chip_name = "raven"; + break; +- case CHIP_PICASSO: +- chip_name = "picasso"; +- break; + default: BUG(); + } + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +index 65aff741befb..a0ae950d3a60 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -2360,7 +2360,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) + break; + #if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case CHIP_RAVEN: +- case CHIP_PICASSO: + #if defined(CONFIG_DRM_AMD_DC_DCN2_0) + case CHIP_NAVI10: + case CHIP_NAVI14: +@@ -2602,7 +2601,6 @@ static int dm_early_init(void *handle) + break; + #if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case CHIP_RAVEN: +- case CHIP_PICASSO: + adev->mode_info.num_crtc = 4; + adev->mode_info.num_hpd = 4; + adev->mode_info.num_dig = 4; +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c +index 873bf65e34d4..e8d4292bc4f0 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c +@@ -173,7 +173,6 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr) + case AMDGPU_FAMILY_RV: + switch (hwmgr->chip_id) { + case CHIP_RAVEN: +- case CHIP_PICASSO: + hwmgr->od_enabled = false; + hwmgr->smumgr_funcs = &smu10_smu_funcs; + smu10_init_function_pointers(hwmgr); +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c +index f6fe9ce793ad..77c14671866c 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c +@@ -832,7 +832,7 @@ static const ATOM_PPLIB_POWERPLAYTABLE *get_powerplay_table( + uint16_t size; + + if (!table_addr) { +- if (hwmgr->chip_id == CHIP_RAVEN || hwmgr->chip_id == CHIP_PICASSO) { ++ if (hwmgr->chip_id == CHIP_RAVEN) { + table_addr = &soft_dummy_pp_table[0]; + hwmgr->soft_pp_table = &soft_dummy_pp_table[0]; + hwmgr->soft_pp_table_size = sizeof(soft_dummy_pp_table); +@@ -1055,7 +1055,7 @@ static int init_overdrive_limits(struct pp_hwmgr *hwmgr, + hwmgr->platform_descriptor.maxOverdriveVDDC = 0; + hwmgr->platform_descriptor.overdriveVDDCStep = 0; + +- if (hwmgr->chip_id == CHIP_RAVEN || hwmgr->chip_id == CHIP_PICASSO) ++ if (hwmgr->chip_id == CHIP_RAVEN) + return 0; + + /* We assume here that fw_info is unchanged if this call fails.*/ +@@ -1595,7 +1595,7 @@ static int pp_tables_initialize(struct pp_hwmgr *hwmgr) + int result; + const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table; + +- if (hwmgr->chip_id == CHIP_RAVEN || hwmgr->chip_id == CHIP_PICASSO) ++ if (hwmgr->chip_id == CHIP_RAVEN) + return 0; + + hwmgr->need_pp_table_upload = true; +@@ -1644,7 +1644,7 @@ static int pp_tables_initialize(struct pp_hwmgr *hwmgr) + + static int pp_tables_uninitialize(struct pp_hwmgr *hwmgr) + { +- if (hwmgr->chip_id == CHIP_RAVEN || hwmgr->chip_id == CHIP_PICASSO) ++ if (hwmgr->chip_id == CHIP_RAVEN) + return 0; + + kfree(hwmgr->dyn_state.vddc_dependency_on_sclk); +diff --git a/include/drm/amd_asic_type.h b/include/drm/amd_asic_type.h +index a4a80ce18a7a..a26d8bcd1a38 100644 +--- a/include/drm/amd_asic_type.h ++++ b/include/drm/amd_asic_type.h +@@ -27,34 +27,33 @@ + */ + enum amd_asic_type { + CHIP_TAHITI = 0, +- CHIP_PITCAIRN, +- CHIP_VERDE, +- CHIP_OLAND, +- CHIP_HAINAN, +- CHIP_BONAIRE, +- CHIP_KAVERI, +- CHIP_KABINI, +- CHIP_HAWAII, +- CHIP_MULLINS, +- CHIP_TOPAZ, +- CHIP_TONGA, +- CHIP_FIJI, +- CHIP_CARRIZO, +- CHIP_STONEY, +- CHIP_POLARIS10, +- CHIP_POLARIS11, +- CHIP_POLARIS12, +- CHIP_VEGAM, +- CHIP_VEGA10, +- CHIP_VEGA12, +- CHIP_VEGA20, +- CHIP_RAVEN, +- CHIP_ARCTURUS, +- CHIP_RENOIR, +- CHIP_PICASSO, +- CHIP_NAVI10, +- CHIP_NAVI14, +- CHIP_NAVI12, ++ CHIP_PITCAIRN, /* 1 */ ++ CHIP_VERDE, /* 2 */ ++ CHIP_OLAND, /* 3 */ ++ CHIP_HAINAN, /* 4 */ ++ CHIP_BONAIRE, /* 5 */ ++ CHIP_KAVERI, /* 6 */ ++ CHIP_KABINI, /* 7 */ ++ CHIP_HAWAII, /* 8 */ ++ CHIP_MULLINS, /* 9 */ ++ CHIP_TOPAZ, /* 10 */ ++ CHIP_TONGA, /* 11 */ ++ CHIP_FIJI, /* 12 */ ++ CHIP_CARRIZO, /* 13 */ ++ CHIP_STONEY, /* 14 */ ++ CHIP_POLARIS10, /* 15 */ ++ CHIP_POLARIS11, /* 16 */ ++ CHIP_POLARIS12, /* 17 */ ++ CHIP_VEGAM, /* 18 */ ++ CHIP_VEGA10, /* 19 */ ++ CHIP_VEGA12, /* 20 */ ++ CHIP_VEGA20, /* 21 */ ++ CHIP_RAVEN, /* 22 */ ++ CHIP_ARCTURUS, /* 23 */ ++ CHIP_RENOIR, /* 24 */ ++ CHIP_NAVI10, /* 25 */ ++ CHIP_NAVI14, /* 26 */ ++ CHIP_NAVI12, /* 27 */ + CHIP_LAST, + }; + +-- +2.17.1 + |