diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3720-drm-amd-display-dce11.x-dce12-update-formula-input.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3720-drm-amd-display-dce11.x-dce12-update-formula-input.patch | 160 |
1 files changed, 160 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3720-drm-amd-display-dce11.x-dce12-update-formula-input.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3720-drm-amd-display-dce11.x-dce12-update-formula-input.patch new file mode 100644 index 00000000..bbe5020f --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3720-drm-amd-display-dce11.x-dce12-update-formula-input.patch @@ -0,0 +1,160 @@ +From 7c4645c4d76b06e69ded4643508b563259d0633f Mon Sep 17 00:00:00 2001 +From: Charlene Liu <charlene.liu@amd.com> +Date: Tue, 20 Aug 2019 20:33:46 -0400 +Subject: [PATCH 3720/4256] drm/amd/display: dce11.x /dce12 update formula + input + +[Description] +1. OUTSTANDING_REQUEST_LIMIT update from 0xFF to 0x1F (HW doc update) +2. using memory type to convert UMC's MCLK to Yclk. + +Signed-off-by: Charlene Liu <charlene.liu@amd.com> +Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +--- + .../display/dc/clk_mgr/dce110/dce110_clk_mgr.c | 7 +++++-- + .../gpu/drm/amd/display/dc/dce/dce_mem_input.c | 4 ++-- + .../drm/amd/display/dc/dce112/dce112_resource.c | 16 ++++++++++------ + .../drm/amd/display/dc/dce120/dce120_resource.c | 11 ++++++++--- + drivers/gpu/drm/amd/display/dc/inc/resource.h | 2 ++ + 5 files changed, 27 insertions(+), 13 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c +index 5cc3acccda2a..ee32d2c19305 100644 +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c +@@ -98,11 +98,14 @@ uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context) + struct dc_stream_state *stream = context->streams[j]; + uint32_t vertical_blank_in_pixels = 0; + uint32_t vertical_blank_time = 0; ++ uint32_t vertical_total_min = stream->timing.v_total; ++ struct dc_crtc_timing_adjust adjust = stream->adjust; ++ if (adjust.v_total_max != adjust.v_total_min) ++ vertical_total_min = adjust.v_total_min; + + vertical_blank_in_pixels = stream->timing.h_total * +- (stream->timing.v_total ++ (vertical_total_min + - stream->timing.v_addressable); +- + vertical_blank_time = vertical_blank_in_pixels + * 10000 / stream->timing.pix_clk_100hz; + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c +index 1488ffddf4e3..31b698bf9cfc 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c +@@ -148,7 +148,7 @@ static void dce_mi_program_pte_vm( + pte->min_pte_before_flip_horiz_scan; + + REG_UPDATE(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, +- GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, 0xff); ++ GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, 0x7f); + + REG_UPDATE_3(DVMM_PTE_CONTROL, + DVMM_PAGE_WIDTH, page_width, +@@ -157,7 +157,7 @@ static void dce_mi_program_pte_vm( + + REG_UPDATE_2(DVMM_PTE_ARB_CONTROL, + DVMM_PTE_REQ_PER_CHUNK, pte->pte_req_per_chunk, +- DVMM_MAX_PTE_REQ_OUTSTANDING, 0xff); ++ DVMM_MAX_PTE_REQ_OUTSTANDING, 0x7f); + } + + static void program_urgency_watermark( +diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +index e327d98b54ca..65f17bbdef2a 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +@@ -985,6 +985,10 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc) + struct dm_pp_clock_levels_with_latency mem_clks = {0}; + struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; + struct dm_pp_clock_levels clks = {0}; ++ int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ; ++ ++ if (dc->bw_vbios && dc->bw_vbios->memory_type == bw_def_hbm) ++ memory_type_multiplier = MEMORY_TYPE_HBM; + + /*do system clock TODO PPLIB: after PPLIB implement, + * then remove old way +@@ -1024,12 +1028,12 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc) + &clks); + + dc->bw_vbios->low_yclk = bw_frc_to_fixed( +- clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER_CZ, 1000); ++ clks.clocks_in_khz[0] * memory_type_multiplier, 1000); + dc->bw_vbios->mid_yclk = bw_frc_to_fixed( +- clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER_CZ, ++ clks.clocks_in_khz[clks.num_levels>>1] * memory_type_multiplier, + 1000); + dc->bw_vbios->high_yclk = bw_frc_to_fixed( +- clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER_CZ, ++ clks.clocks_in_khz[clks.num_levels-1] * memory_type_multiplier, + 1000); + + return; +@@ -1065,12 +1069,12 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc) + * YCLK = UMACLK*m_memoryTypeMultiplier + */ + dc->bw_vbios->low_yclk = bw_frc_to_fixed( +- mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 1000); ++ mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000); + dc->bw_vbios->mid_yclk = bw_frc_to_fixed( +- mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, ++ mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier, + 1000); + dc->bw_vbios->high_yclk = bw_frc_to_fixed( +- mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, ++ mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier, + 1000); + + /* Now notify PPLib/SMU about which Watermarks sets they should select +diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +index c4588d6462a4..c10392bbcb38 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +@@ -845,6 +845,8 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc) + int i; + unsigned int clk; + unsigned int latency; ++ /*original logic in dal3*/ ++ int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ; + + /*do system clock*/ + if (!dm_pp_get_clock_levels_by_type_with_latency( +@@ -903,13 +905,16 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc) + * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): + * YCLK = UMACLK*m_memoryTypeMultiplier + */ ++ if (dc->bw_vbios->memory_type == bw_def_hbm) ++ memory_type_multiplier = MEMORY_TYPE_HBM; ++ + dc->bw_vbios->low_yclk = bw_frc_to_fixed( +- mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 1000); ++ mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000); + dc->bw_vbios->mid_yclk = bw_frc_to_fixed( +- mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, ++ mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier, + 1000); + dc->bw_vbios->high_yclk = bw_frc_to_fixed( +- mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, ++ mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier, + 1000); + + /* Now notify PPLib/SMU about which Watermarks sets they should select +diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h +index 1cc1c8ce633b..bef224bf803e 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h +@@ -31,6 +31,8 @@ + #include "dm_pp_smu.h" + + #define MEMORY_TYPE_MULTIPLIER_CZ 4 ++#define MEMORY_TYPE_HBM 2 ++ + + enum dce_version resource_parse_asic_id( + struct hw_asic_id asic_id); +-- +2.17.1 + |