diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3717-drm-amd-display-remove-hw-access-from-dc_destroy.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3717-drm-amd-display-remove-hw-access-from-dc_destroy.patch | 204 |
1 files changed, 204 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3717-drm-amd-display-remove-hw-access-from-dc_destroy.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3717-drm-amd-display-remove-hw-access-from-dc_destroy.patch new file mode 100644 index 00000000..9291d42c --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3717-drm-amd-display-remove-hw-access-from-dc_destroy.patch @@ -0,0 +1,204 @@ +From a90d4c92c221200b6b9376d5aca2c1e41e96595e Mon Sep 17 00:00:00 2001 +From: Jun Lei <Jun.Lei@amd.com> +Date: Thu, 15 Aug 2019 15:22:34 -0400 +Subject: [PATCH 3717/4256] drm/amd/display: remove hw access from dc_destroy + +[why] +dc_destroy should only clean up SW, this is because GPUs may be +removed before driver unload, leading to HW to be unavailable. + +[how] +remove GPIO close as part of GPIO destroy, this is unnecessary because +GPIO is not shared, and GPIOs are generally closed after being opened + +Add tracking to HW access during destructor to make future issues +easier to pinpoint, and block access to prevent hangs. + +Signed-off-by: Jun Lei <Jun.Lei@amd.com> +Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> +Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +--- + .../display/dc/clk_mgr/dcn10/rv1_clk_mgr.c | 3 +++ + drivers/gpu/drm/amd/display/dc/core/dc.c | 20 +++++++++++++------ + drivers/gpu/drm/amd/display/dc/core/dc_link.c | 1 - + drivers/gpu/drm/amd/display/dc/dc.h | 6 ++---- + drivers/gpu/drm/amd/display/dc/dc_stream.h | 2 ++ + drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | 3 --- + drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 3 --- + .../gpu/drm/amd/display/dc/gpio/gpio_base.c | 2 -- + .../drm/amd/display/dc/gpio/gpio_service.c | 2 -- + 9 files changed, 21 insertions(+), 21 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c +index d00ee9fa04e4..6e03805e1b87 100644 +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c +@@ -136,6 +136,9 @@ static void rv1_update_clocks(struct clk_mgr *clk_mgr_base, + + ASSERT(clk_mgr->pp_smu); + ++ if (dc->work_arounds.skip_clock_update) ++ return; ++ + pp_smu = &clk_mgr->pp_smu->rv_funcs; + + display_count = clk_mgr_helper_get_active_display_cnt(dc, context); +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index 17990586e704..1139a365aa8d 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -1895,6 +1895,7 @@ static void commit_planes_do_stream_update(struct dc *dc, + struct dc_state *context) + { + int j; ++ bool should_program_abm; + + // Stream updates + for (j = 0; j < dc->res_pool->pipe_count; j++) { +@@ -1975,14 +1976,21 @@ static void commit_planes_do_stream_update(struct dc *dc, + } + + if (stream_update->abm_level && pipe_ctx->stream_res.abm) { +- if (pipe_ctx->stream_res.tg->funcs->is_blanked) { +- // if otg funcs defined check if blanked before programming +- if (!pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) ++ should_program_abm = true; ++ ++ // if otg funcs defined check if blanked before programming ++ if (pipe_ctx->stream_res.tg->funcs->is_blanked) ++ if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) ++ should_program_abm = false; ++ ++ if (should_program_abm) { ++ if (*stream_update->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) { ++ pipe_ctx->stream_res.abm->funcs->set_abm_immediate_disable(pipe_ctx->stream_res.abm); ++ } else { + pipe_ctx->stream_res.abm->funcs->set_abm_level( + pipe_ctx->stream_res.abm, stream->abm_level); +- } else +- pipe_ctx->stream_res.abm->funcs->set_abm_level( +- pipe_ctx->stream_res.abm, stream->abm_level); ++ } ++ } + } + } + } +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c +index 94734c22bbde..fcc25eea0d8f 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c +@@ -77,7 +77,6 @@ static void destruct(struct dc_link *link) + int i; + + if (link->hpd_gpio != NULL) { +- dal_gpio_close(link->hpd_gpio); + dal_gpio_destroy_irq(&link->hpd_gpio); + link->hpd_gpio = NULL; + } +diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h +index ab1759f08dbd..3bb4d41ffdb4 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc.h ++++ b/drivers/gpu/drm/amd/display/dc/dc.h +@@ -120,13 +120,13 @@ struct dc_caps { + struct dc_plane_cap planes[MAX_PLANES]; + }; + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + struct dc_bug_wa { ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + bool no_connect_phy_config; + bool dedcn20_305_wa; ++#endif + bool skip_clock_update; + }; +-#endif + + struct dc_dcc_surface_param { + struct dc_size surface_size; +@@ -466,9 +466,7 @@ struct dc { + struct dc_config config; + struct dc_debug_options debug; + struct dc_bounding_box_overrides bb_overrides; +-#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + struct dc_bug_wa work_arounds; +-#endif + struct dc_context *ctx; + #ifdef CONFIG_DRM_AMD_DC_DCN2_0 + struct dc_phy_addr_space_config vm_pa_config; +diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h +index e2d9e11be4b0..3c061d4f214f 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h ++++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h +@@ -232,6 +232,8 @@ struct dc_stream_state { + union stream_update_flags update_flags; + }; + ++#define ABM_LEVEL_IMMEDIATE_DISABLE 0xFFFFFFFF ++ + struct dc_stream_update { + struct dc_stream_state *stream; + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c +index adde7a5760bc..b5c97b313c54 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c +@@ -487,9 +487,6 @@ void dce_abm_destroy(struct abm **abm) + { + struct dce_abm *abm_dce = TO_DCE_ABM(*abm); + +- if (abm_dce->base.dmcu_is_running == true) +- abm_dce->base.funcs->set_abm_immediate_disable(*abm); +- + kfree(abm_dce); + *abm = NULL; + } +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +index f3b01f0b8ce7..f86ad9865a48 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +@@ -904,9 +904,6 @@ void dce_dmcu_destroy(struct dmcu **dmcu) + { + struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu); + +- if (dmcu_dce->base.dmcu_state == DMCU_RUNNING) +- dmcu_dce->base.funcs->set_psr_enable(*dmcu, false, true); +- + kfree(dmcu_dce); + *dmcu = NULL; + } +diff --git a/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c b/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c +index c6f1a7c3affd..c85f21bf07d9 100644 +--- a/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c ++++ b/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c +@@ -319,8 +319,6 @@ void dal_gpio_destroy( + return; + } + +- dal_gpio_close(*gpio); +- + switch ((*gpio)->id) { + case GPIO_ID_DDC_DATA: + kfree((*gpio)->hw_container.ddc); +diff --git a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c b/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c +index 30028223f8bc..2a153fb9a62a 100644 +--- a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c ++++ b/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c +@@ -167,7 +167,6 @@ void dal_gpio_destroy_generic_mux( + return; + } + +- dal_gpio_close(*mux); + dal_gpio_destroy(mux); + kfree(*mux); + +@@ -458,7 +457,6 @@ void dal_gpio_destroy_irq( + return; + } + +- dal_gpio_close(*irq); + dal_gpio_destroy(irq); + kfree(*irq); + +-- +2.17.1 + |