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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3695-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-nbio-v.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3695-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-nbio-v.patch57
1 files changed, 57 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3695-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-nbio-v.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3695-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-nbio-v.patch
new file mode 100644
index 00000000..5042ff06
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3695-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-nbio-v.patch
@@ -0,0 +1,57 @@
+From 91dbf0f415f9f3965df78c1b343e789612689fdc Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Thu, 29 Aug 2019 19:56:44 +0800
+Subject: [PATCH 3695/4256] drm/amdgpu: switch to amdgpu_ras_late_init for nbio
+ v7_4 (v2)
+
+call helper function in late init phase to handle ras init
+for nbio ip block
+
+v2: init local var r to 0 in case the function return failure
+on asics that don't have ras_late_init implementation
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 13 ++++++++++++-
+ 1 file changed, 12 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 45518ef8c656..cb22970c0853 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1214,11 +1214,15 @@ static int soc15_common_early_init(void *handle)
+ static int soc15_common_late_init(void *handle)
+ {
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++ int r = 0;
+
+ if (amdgpu_sriov_vf(adev))
+ xgpu_ai_mailbox_get_irq(adev);
+
+- return 0;
++ if (adev->nbio.funcs->ras_late_init)
++ r = adev->nbio.funcs->ras_late_init(adev);
++
++ return r;
+ }
+
+ static int soc15_common_sw_init(void *handle)
+@@ -1298,6 +1302,13 @@ static int soc15_common_hw_fini(void *handle)
+ if (amdgpu_sriov_vf(adev))
+ xgpu_ai_mailbox_put_irq(adev);
+
++ if (amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
++ if (adev->nbio.funcs->init_ras_controller_interrupt)
++ amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
++ if (adev->nbio.funcs->init_ras_err_event_athub_interrupt)
++ amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
++ }
++
+ return 0;
+ }
+
+--
+2.17.1
+