diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3669-drm-amd-powerplay-guard-manual-mode-prerequisite-for.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3669-drm-amd-powerplay-guard-manual-mode-prerequisite-for.patch | 92 |
1 files changed, 92 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3669-drm-amd-powerplay-guard-manual-mode-prerequisite-for.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3669-drm-amd-powerplay-guard-manual-mode-prerequisite-for.patch new file mode 100644 index 00000000..50f5a3db --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3669-drm-amd-powerplay-guard-manual-mode-prerequisite-for.patch @@ -0,0 +1,92 @@ +From fac4d902a25b294c4a595c7c20c2c76f932c504d Mon Sep 17 00:00:00 2001 +From: Evan Quan <evan.quan@amd.com> +Date: Fri, 30 Aug 2019 17:30:46 +0800 +Subject: [PATCH 3669/4256] drm/amd/powerplay: guard manual mode prerequisite + for clock level force + +Force clock level is for dpm manual mode only. + +Change-Id: I3b4caf3fafc72197d65e2b9255c68e40e673e25e +Reported-by: Candice Li <candice.li@amd.com> +Signed-off-by: Evan Quan <evan.quan@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +Reviewed-by: Jack Gui <Jack.Gui@amd.com> +--- + drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 18 ++++++++++++++++++ + drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 5 +++-- + drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 6 ------ + 3 files changed, 21 insertions(+), 8 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +index a9cce9985d16..04731351b194 100644 +--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c ++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +@@ -1756,6 +1756,24 @@ int smu_set_display_count(struct smu_context *smu, uint32_t count) + return ret; + } + ++int smu_force_clk_levels(struct smu_context *smu, ++ enum smu_clk_type clk_type, ++ uint32_t mask) ++{ ++ struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); ++ int ret = 0; ++ ++ if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { ++ pr_debug("force clock level is for dpm manual mode only.\n"); ++ return -EINVAL; ++ } ++ ++ if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) ++ ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); ++ ++ return ret; ++} ++ + const struct amd_ip_funcs smu_ip_funcs = { + .name = "smu", + .early_init = smu_early_init, +diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +index 32cd2074178d..83e35c990300 100644 +--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h ++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +@@ -634,8 +634,6 @@ struct smu_funcs + ((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0) + #define smu_print_clk_levels(smu, clk_type, buf) \ + ((smu)->ppt_funcs->print_clk_levels ? (smu)->ppt_funcs->print_clk_levels((smu), (clk_type), (buf)) : 0) +-#define smu_force_clk_levels(smu, clk_type, level) \ +- ((smu)->ppt_funcs->force_clk_levels ? (smu)->ppt_funcs->force_clk_levels((smu), (clk_type), (level)) : 0) + #define smu_get_od_percentage(smu, type) \ + ((smu)->ppt_funcs->get_od_percentage ? (smu)->ppt_funcs->get_od_percentage((smu), (type)) : 0) + #define smu_set_od_percentage(smu, type, value) \ +@@ -833,5 +831,8 @@ const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type + const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature); + size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf); + int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask); ++int smu_force_clk_levels(struct smu_context *smu, ++ enum smu_clk_type clk_type, ++ uint32_t mask); + + #endif +diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c +index 68548ba9b6ea..18d1b432f719 100644 +--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c ++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c +@@ -1274,14 +1274,8 @@ static int vega20_force_clk_levels(struct smu_context *smu, + struct vega20_dpm_table *dpm_table; + struct vega20_single_dpm_table *single_dpm_table; + uint32_t soft_min_level, soft_max_level, hard_min_level; +- struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + int ret = 0; + +- if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { +- pr_info("force clock level is for dpm manual mode only.\n"); +- return -EINVAL; +- } +- + mutex_lock(&(smu->mutex)); + + soft_min_level = mask ? (ffs(mask) - 1) : 0; +-- +2.17.1 + |