diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3668-drm-amdgpu-Remove-unnecessary-TLB-workaround-v2.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3668-drm-amdgpu-Remove-unnecessary-TLB-workaround-v2.patch | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3668-drm-amdgpu-Remove-unnecessary-TLB-workaround-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3668-drm-amdgpu-Remove-unnecessary-TLB-workaround-v2.patch new file mode 100644 index 00000000..d0a3bc88 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3668-drm-amdgpu-Remove-unnecessary-TLB-workaround-v2.patch @@ -0,0 +1,76 @@ +From 8e570139eb21b7db16e953cca590d16ba0f12c8f Mon Sep 17 00:00:00 2001 +From: Felix Kuehling <Felix.Kuehling@amd.com> +Date: Thu, 29 Aug 2019 21:18:43 -0400 +Subject: [PATCH 3668/4256] drm/amdgpu: Remove unnecessary TLB workaround (v2) +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This workaround is better handled in user mode in a way that doesn't +require allocating extra memory and breaking userptr BOs. + +The TLB bug is a performance bug, not a functional or security bug. +Hence it is safe to remove this kernel part of the workaround to +allow a better workaround using only virtual address alignments in +user mode. + +v2: Removed VI_BO_SIZE_ALIGN definition + +Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> +Reviewed-by: Christian König <christian.koenig@amd.com> +--- + .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 17 +---------------- + 1 file changed, 1 insertion(+), 16 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +index 580f52eda694..7da67e5b3140 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +@@ -33,11 +33,6 @@ + #include "amdgpu_amdkfd.h" + #include "amdgpu_dma_buf.h" + +-/* Special VM and GART address alignment needed for VI pre-Fiji due to +- * a HW bug. +- */ +-#define VI_BO_SIZE_ALIGN (0x8000) +- + /* BO flag to indicate a KFD userptr BO */ + #define AMDGPU_AMDKFD_USERPTR_BO (1ULL << 63) + +@@ -1138,7 +1133,6 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( + uint64_t user_addr = 0; + struct amdgpu_bo *bo; + struct amdgpu_bo_param bp; +- int byte_align; + u32 domain, alloc_domain; + u64 alloc_flags; + uint32_t mapping_flags; +@@ -1201,15 +1195,6 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( + if ((*mem)->aql_queue) + size = size >> 1; + +- /* Workaround for TLB bug on older VI chips */ +- byte_align = (adev->family == AMDGPU_FAMILY_VI && +- adev->asic_type != CHIP_FIJI && +- adev->asic_type != CHIP_POLARIS10 && +- adev->asic_type != CHIP_POLARIS11 && +- adev->asic_type != CHIP_POLARIS12 && +- adev->asic_type != CHIP_VEGAM) ? +- VI_BO_SIZE_ALIGN : 1; +- + mapping_flags = AMDGPU_VM_PAGE_READABLE; + if (flags & ALLOC_MEM_FLAGS_WRITABLE) + mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE; +@@ -1235,7 +1220,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( + + memset(&bp, 0, sizeof(bp)); + bp.size = size; +- bp.byte_align = byte_align; ++ bp.byte_align = 1; + bp.domain = alloc_domain; + bp.flags = alloc_flags; + bp.type = bo_type; +-- +2.17.1 + |