diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3666-drm-amdgpu-fix-no-interrupt-issue-for-renoir-emu-v2.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3666-drm-amdgpu-fix-no-interrupt-issue-for-renoir-emu-v2.patch | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3666-drm-amdgpu-fix-no-interrupt-issue-for-renoir-emu-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3666-drm-amdgpu-fix-no-interrupt-issue-for-renoir-emu-v2.patch new file mode 100644 index 00000000..744830f0 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3666-drm-amdgpu-fix-no-interrupt-issue-for-renoir-emu-v2.patch @@ -0,0 +1,59 @@ +From 3efe1818511639401abd79759daaf1e651ec96a6 Mon Sep 17 00:00:00 2001 +From: Aaron Liu <aaron.liu@amd.com> +Date: Fri, 14 Dec 2018 11:21:41 +0800 +Subject: [PATCH 3666/4256] drm/amdgpu: fix no interrupt issue for renoir emu + (v2) + +In renoir's vega10_ih model, there's a security change in mmIH_CHICKEN +register, that limits IH to use physical address (FBPA, GPA) directly. +Those chicken bits need to be programmed first. + +Signed-off-by: Aaron Liu <aaron.liu@amd.com> +Reviewed-by: Huang Rui <ray.huang@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 18 ++++++++++-------- + 1 file changed, 10 insertions(+), 8 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +index d92ff25f1ed3..d7135e5871d4 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c ++++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +@@ -232,7 +232,13 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) + WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff); + + ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); ++ ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); + ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); ++ if (adev->irq.ih.use_bus_addr) { ++ ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); ++ } else { ++ ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, MC_SPACE_FBPA_ENABLE, 1); ++ } + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, + !!adev->irq.msi_enabled); + +@@ -245,14 +251,10 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); + } + +- if ((adev->asic_type == CHIP_ARCTURUS || adev->asic_type == CHIP_RENOIR) && +- adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { +- if (adev->irq.ih.use_bus_addr) { +- ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); +- ih_chicken |= 0x00000010; +- WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); +- } +- } ++ if ((adev->asic_type == CHIP_ARCTURUS ++ && adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) ++ || adev->asic_type == CHIP_RENOIR) ++ WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); + + /* set the writeback address whether it's enabled or not */ + WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, +-- +2.17.1 + |