diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3665-drm-amdgpu-update-IH_CHICKEN-in-oss-4.0-IP-header-fo.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3665-drm-amdgpu-update-IH_CHICKEN-in-oss-4.0-IP-header-fo.patch | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3665-drm-amdgpu-update-IH_CHICKEN-in-oss-4.0-IP-header-fo.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3665-drm-amdgpu-update-IH_CHICKEN-in-oss-4.0-IP-header-fo.patch new file mode 100644 index 00000000..50b011c8 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3665-drm-amdgpu-update-IH_CHICKEN-in-oss-4.0-IP-header-fo.patch @@ -0,0 +1,36 @@ +From ad154d9a300dbb2c10699c699afe07e0474eaffa Mon Sep 17 00:00:00 2001 +From: Aaron Liu <aaron.liu@amd.com> +Date: Fri, 14 Dec 2018 11:16:36 +0800 +Subject: [PATCH 3665/4256] drm/amdgpu: update IH_CHICKEN in oss 4.0 IP header + for VG/RV series + +In Renoir's emulator, those chicken bits need to be programmed. + +Signed-off-by: Aaron Liu <aaron.liu@amd.com> +Reviewed-by: Huang Rui <ray.huang@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h +index 1ee3a2329ee4..dc9895a684fe 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h +@@ -1109,7 +1109,11 @@ + #define IH_CID_REMAP_DATA__CLIENT_ID_REMAP_MASK 0x00FF0000L + //IH_CHICKEN + #define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE__SHIFT 0x0 ++#define IH_CHICKEN__MC_SPACE_FBPA_ENABLE__SHIFT 0x3 ++#define IH_CHICKEN__MC_SPACE_GPA_ENABLE__SHIFT 0x4 + #define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE_MASK 0x00000001L ++#define IH_CHICKEN__MC_SPACE_FBPA_ENABLE_MASK 0x00000008L ++#define IH_CHICKEN__MC_SPACE_GPA_ENABLE_MASK 0x00000010L + //IH_MMHUB_CNTL + #define IH_MMHUB_CNTL__UNITID__SHIFT 0x0 + #define IH_MMHUB_CNTL__IV_TLVL__SHIFT 0x8 +-- +2.17.1 + |