diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3648-drm-amd-display-add-dcn21-core-DC-changes.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3648-drm-amd-display-add-dcn21-core-DC-changes.patch | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3648-drm-amd-display-add-dcn21-core-DC-changes.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3648-drm-amd-display-add-dcn21-core-DC-changes.patch new file mode 100644 index 00000000..ace78808 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3648-drm-amd-display-add-dcn21-core-DC-changes.patch @@ -0,0 +1,76 @@ +From fb4d04659221573784f9f4d51c125b54a180e48d Mon Sep 17 00:00:00 2001 +From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Date: Fri, 26 Jul 2019 17:16:47 -0400 +Subject: [PATCH 3648/4256] drm/amd/display: add dcn21 core DC changes + +Add missing parameters, to make dcn21 compile +without errors + +Acked-by: Harry Wentland <harry.wentland@amd.com> +Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dc.h | 3 +++ + drivers/gpu/drm/amd/display/dc/inc/core_types.h | 3 +++ + drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 4 ++++ + drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 1 + + 4 files changed, 11 insertions(+) + +diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h +index dcb2d4505c58..9e006ad6fa47 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc.h ++++ b/drivers/gpu/drm/amd/display/dc/dc.h +@@ -388,6 +388,9 @@ struct dc_debug_options { + struct dc_bw_validation_profile bw_val_profile; + #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + bool disable_fec; ++#endif ++#ifdef CONFIG_DRM_AMD_DC_DCN2_1 ++ bool disable_48mhz_pwrdwn; + #endif + /* This forces a hard min on the DCFCLK requested to SMU/PP + * watermarks are not affected. +diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h +index 8726bd7dd910..f189307750ab 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h +@@ -87,6 +87,9 @@ void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); + struct resource_pool; + struct dc_state; + struct resource_context; ++#if defined(CONFIG_DRM_AMD_DC_DCN2_1) ++struct clk_bw_params; ++#endif + + struct resource_funcs { + void (*destroy)(struct resource_pool **pool); +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +index 7193acfcd779..e8668388581b 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +@@ -40,6 +40,10 @@ struct cstate_pstate_watermarks_st { + struct dcn_watermarks { + uint32_t pte_meta_urgent_ns; + uint32_t urgent_ns; ++#if defined(CONFIG_DRM_AMD_DC_DCN2_1) ++ uint32_t frac_urg_bw_nom; ++ uint32_t frac_urg_bw_flip; ++#endif + struct cstate_pstate_watermarks_st cstate_pstate; + }; + +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +index 732a93df1844..3a938cd414ea 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +@@ -48,6 +48,7 @@ struct dce_hwseq_wa { + bool DEGVIDCN10_253; + bool false_optc_underflow; + bool DEGVIDCN10_254; ++ bool DEGVIDCN21; + }; + + struct hwseq_wa_state { +-- +2.17.1 + |