diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3638-drm-amd-display-Add-Renoir-Hubbub-v2.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3638-drm-amd-display-Add-Renoir-Hubbub-v2.patch | 775 |
1 files changed, 775 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3638-drm-amd-display-Add-Renoir-Hubbub-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3638-drm-amd-display-Add-Renoir-Hubbub-v2.patch new file mode 100644 index 00000000..f5b8cc56 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3638-drm-amd-display-Add-Renoir-Hubbub-v2.patch @@ -0,0 +1,775 @@ +From dd880233bc85bb1d8dc42317fd7d909eb0546e50 Mon Sep 17 00:00:00 2001 +From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Date: Thu, 25 Jul 2019 16:31:50 -0400 +Subject: [PATCH 3638/4256] drm/amd/display: Add Renoir Hubbub (v2) + +Controls the display hw's interface to memory. + +v2: rebase (Alex) + +Acked-by: Harry Wentland <harry.wentland@amd.com> +Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 2 +- + .../drm/amd/display/dc/dcn21/dcn21_hubbub.c | 595 ++++++++++++++++++ + .../drm/amd/display/dc/dcn21/dcn21_hubbub.h | 132 ++++ + 3 files changed, 728 insertions(+), 1 deletion(-) + create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c + create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile +index d43f866930be..32764714e2b0 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile ++++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile +@@ -1,7 +1,7 @@ + # + # Makefile for DCN21. + +-DCN21 = dcn21_hubp.o ++DCN21 = dcn21_hubp.o dcn21_hubbub.o + + CFLAGS_dcn21_resource.o := -mhard-float -msse -mpreferred-stack-boundary=4 + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c +new file mode 100644 +index 000000000000..d1266741763b +--- /dev/null ++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c +@@ -0,0 +1,595 @@ ++/* ++* Copyright 2018 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: AMD ++ * ++ */ ++#include "dm_services.h" ++#include "dcn20/dcn20_hubbub.h" ++#include "dcn21_hubbub.h" ++#include "reg_helper.h" ++ ++#define REG(reg)\ ++ hubbub1->regs->reg ++#define DC_LOGGER \ ++ hubbub1->base.ctx->logger ++#define CTX \ ++ hubbub1->base.ctx ++ ++#undef FN ++#define FN(reg_name, field_name) \ ++ hubbub1->shifts->field_name, hubbub1->masks->field_name ++ ++#define REG(reg)\ ++ hubbub1->regs->reg ++ ++#define CTX \ ++ hubbub1->base.ctx ++ ++#undef FN ++#define FN(reg_name, field_name) \ ++ hubbub1->shifts->field_name, hubbub1->masks->field_name ++ ++#ifdef NUM_VMID ++#undef NUM_VMID ++#endif ++#define NUM_VMID 1 ++ ++static uint32_t convert_and_clamp( ++ uint32_t wm_ns, ++ uint32_t refclk_mhz, ++ uint32_t clamp_value) ++{ ++ uint32_t ret_val = 0; ++ ret_val = wm_ns * refclk_mhz; ++ ret_val /= 1000; ++ ++ if (ret_val > clamp_value) ++ ret_val = clamp_value; ++ ++ return ret_val; ++} ++ ++void dcn21_dchvm_init(struct hubbub *hubbub) ++{ ++ struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); ++ ++ //Init DCHVM block ++ REG_UPDATE(DCHVM_CTRL0, HOSTVM_INIT_REQ, 1); ++ ++ //Poll until RIOMMU_ACTIVE = 1 ++ //TODO: Figure out interval us and retry count ++ REG_WAIT(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, 1, 5, 100); ++ ++ //Reflect the power status of DCHUBBUB ++ REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, 1); ++ ++ //Start rIOMMU prefetching ++ REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, 1); ++ ++ // Enable dynamic clock gating ++ REG_UPDATE_4(DCHVM_CLK_CTRL, ++ HVM_DISPCLK_R_GATE_DIS, 0, ++ HVM_DISPCLK_G_GATE_DIS, 0, ++ HVM_DCFCLK_R_GATE_DIS, 0, ++ HVM_DCFCLK_G_GATE_DIS, 0); ++ ++ //Poll until HOSTVM_PREFETCH_DONE = 1 ++ //TODO: Figure out interval us and retry count ++ REG_WAIT(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, 1, 5, 100); ++} ++ ++static int hubbub21_init_dchub(struct hubbub *hubbub, ++ struct dcn_hubbub_phys_addr_config *pa_config) ++{ ++ struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); ++ ++ REG_SET(DCN_VM_FB_LOCATION_BASE, 0, ++ FB_BASE, pa_config->system_aperture.fb_base); ++ REG_SET(DCN_VM_FB_LOCATION_TOP, 0, ++ FB_TOP, pa_config->system_aperture.fb_top); ++ REG_SET(DCN_VM_FB_OFFSET, 0, ++ FB_OFFSET, pa_config->system_aperture.fb_offset); ++ REG_SET(DCN_VM_AGP_BOT, 0, ++ AGP_BOT, pa_config->system_aperture.agp_bot); ++ REG_SET(DCN_VM_AGP_TOP, 0, ++ AGP_TOP, pa_config->system_aperture.agp_top); ++ REG_SET(DCN_VM_AGP_BASE, 0, ++ AGP_BASE, pa_config->system_aperture.agp_base); ++ ++ dcn21_dchvm_init(hubbub); ++ ++ return NUM_VMID; ++} ++ ++static void hubbub21_program_urgent_watermarks( ++ struct hubbub *hubbub, ++ struct dcn_watermark_set *watermarks, ++ unsigned int refclk_mhz, ++ bool safe_to_lower) ++{ ++ struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); ++ uint32_t prog_wm_value; ++ ++ /* Repeat for water mark set A, B, C and D. */ ++ /* clock state A */ ++ if (safe_to_lower || watermarks->a.urgent_ns > hubbub1->watermarks.a.urgent_ns) { ++ hubbub1->watermarks.a.urgent_ns = watermarks->a.urgent_ns; ++ prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns, ++ refclk_mhz, 0x1fffff); ++ REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0, ++ DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value, ++ DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A, prog_wm_value); ++ ++ DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_A calculated =%d\n" ++ "HW register value = 0x%x\n", ++ watermarks->a.urgent_ns, prog_wm_value); ++ } ++ ++ /* determine the transfer time for a quantity of data for a particular requestor.*/ ++ if (safe_to_lower || watermarks->a.frac_urg_bw_flip ++ > hubbub1->watermarks.a.frac_urg_bw_flip) { ++ hubbub1->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip; ++ ++ REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0, ++ DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, watermarks->a.frac_urg_bw_flip); ++ } ++ ++ if (safe_to_lower || watermarks->a.frac_urg_bw_nom ++ > hubbub1->watermarks.a.frac_urg_bw_nom) { ++ hubbub1->watermarks.a.frac_urg_bw_nom = watermarks->a.frac_urg_bw_nom; ++ ++ REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0, ++ DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, watermarks->a.frac_urg_bw_nom); ++ } ++ ++ /* clock state B */ ++ if (safe_to_lower || watermarks->b.urgent_ns > hubbub1->watermarks.b.urgent_ns) { ++ hubbub1->watermarks.b.urgent_ns = watermarks->b.urgent_ns; ++ prog_wm_value = convert_and_clamp(watermarks->b.urgent_ns, ++ refclk_mhz, 0x1fffff); ++ REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0, ++ DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value, ++ DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B, prog_wm_value); ++ ++ DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_B calculated =%d\n" ++ "HW register value = 0x%x\n", ++ watermarks->b.urgent_ns, prog_wm_value); ++ } ++ ++ /* determine the transfer time for a quantity of data for a particular requestor.*/ ++ if (safe_to_lower || watermarks->a.frac_urg_bw_flip ++ > hubbub1->watermarks.a.frac_urg_bw_flip) { ++ hubbub1->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip; ++ ++ REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, 0, ++ DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, watermarks->a.frac_urg_bw_flip); ++ } ++ ++ if (safe_to_lower || watermarks->a.frac_urg_bw_nom ++ > hubbub1->watermarks.a.frac_urg_bw_nom) { ++ hubbub1->watermarks.a.frac_urg_bw_nom = watermarks->a.frac_urg_bw_nom; ++ ++ REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, 0, ++ DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, watermarks->a.frac_urg_bw_nom); ++ } ++ ++ /* clock state C */ ++ if (safe_to_lower || watermarks->c.urgent_ns > hubbub1->watermarks.c.urgent_ns) { ++ hubbub1->watermarks.c.urgent_ns = watermarks->c.urgent_ns; ++ prog_wm_value = convert_and_clamp(watermarks->c.urgent_ns, ++ refclk_mhz, 0x1fffff); ++ REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0, ++ DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value, ++ DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C, prog_wm_value); ++ ++ DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_C calculated =%d\n" ++ "HW register value = 0x%x\n", ++ watermarks->c.urgent_ns, prog_wm_value); ++ } ++ ++ /* determine the transfer time for a quantity of data for a particular requestor.*/ ++ if (safe_to_lower || watermarks->a.frac_urg_bw_flip ++ > hubbub1->watermarks.a.frac_urg_bw_flip) { ++ hubbub1->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip; ++ ++ REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, 0, ++ DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, watermarks->a.frac_urg_bw_flip); ++ } ++ ++ if (safe_to_lower || watermarks->a.frac_urg_bw_nom ++ > hubbub1->watermarks.a.frac_urg_bw_nom) { ++ hubbub1->watermarks.a.frac_urg_bw_nom = watermarks->a.frac_urg_bw_nom; ++ ++ REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, 0, ++ DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, watermarks->a.frac_urg_bw_nom); ++ } ++ ++ /* clock state D */ ++ if (safe_to_lower || watermarks->d.urgent_ns > hubbub1->watermarks.d.urgent_ns) { ++ hubbub1->watermarks.d.urgent_ns = watermarks->d.urgent_ns; ++ prog_wm_value = convert_and_clamp(watermarks->d.urgent_ns, ++ refclk_mhz, 0x1fffff); ++ REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0, ++ DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value, ++ DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D, prog_wm_value); ++ ++ DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_D calculated =%d\n" ++ "HW register value = 0x%x\n", ++ watermarks->d.urgent_ns, prog_wm_value); ++ } ++ ++ /* determine the transfer time for a quantity of data for a particular requestor.*/ ++ if (safe_to_lower || watermarks->a.frac_urg_bw_flip ++ > hubbub1->watermarks.a.frac_urg_bw_flip) { ++ hubbub1->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip; ++ ++ REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, 0, ++ DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, watermarks->a.frac_urg_bw_flip); ++ } ++ ++ if (safe_to_lower || watermarks->a.frac_urg_bw_nom ++ > hubbub1->watermarks.a.frac_urg_bw_nom) { ++ hubbub1->watermarks.a.frac_urg_bw_nom = watermarks->a.frac_urg_bw_nom; ++ ++ REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, 0, ++ DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, watermarks->a.frac_urg_bw_nom); ++ } ++} ++ ++static void hubbub21_program_stutter_watermarks( ++ struct hubbub *hubbub, ++ struct dcn_watermark_set *watermarks, ++ unsigned int refclk_mhz, ++ bool safe_to_lower) ++{ ++ struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); ++ uint32_t prog_wm_value; ++ ++ /* clock state A */ ++ if (safe_to_lower || watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns ++ > hubbub1->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns) { ++ hubbub1->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = ++ watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns; ++ prog_wm_value = convert_and_clamp( ++ watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, ++ refclk_mhz, 0x1fffff); ++ REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0, ++ DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value, ++ DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value); ++ DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_A calculated =%d\n" ++ "HW register value = 0x%x\n", ++ watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); ++ } ++ ++ if (safe_to_lower || watermarks->a.cstate_pstate.cstate_exit_ns ++ > hubbub1->watermarks.a.cstate_pstate.cstate_exit_ns) { ++ hubbub1->watermarks.a.cstate_pstate.cstate_exit_ns = ++ watermarks->a.cstate_pstate.cstate_exit_ns; ++ prog_wm_value = convert_and_clamp( ++ watermarks->a.cstate_pstate.cstate_exit_ns, ++ refclk_mhz, 0x1fffff); ++ REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0, ++ DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value, ++ DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value); ++ DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_A calculated =%d\n" ++ "HW register value = 0x%x\n", ++ watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value); ++ } ++ ++ /* clock state B */ ++ if (safe_to_lower || watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns ++ > hubbub1->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns) { ++ hubbub1->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = ++ watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns; ++ prog_wm_value = convert_and_clamp( ++ watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, ++ refclk_mhz, 0x1fffff); ++ REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0, ++ DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value, ++ DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value); ++ DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_B calculated =%d\n" ++ "HW register value = 0x%x\n", ++ watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); ++ } ++ ++ if (safe_to_lower || watermarks->b.cstate_pstate.cstate_exit_ns ++ > hubbub1->watermarks.b.cstate_pstate.cstate_exit_ns) { ++ hubbub1->watermarks.b.cstate_pstate.cstate_exit_ns = ++ watermarks->b.cstate_pstate.cstate_exit_ns; ++ prog_wm_value = convert_and_clamp( ++ watermarks->b.cstate_pstate.cstate_exit_ns, ++ refclk_mhz, 0x1fffff); ++ REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0, ++ DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value, ++ DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value); ++ DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_B calculated =%d\n" ++ "HW register value = 0x%x\n", ++ watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value); ++ } ++ ++ /* clock state C */ ++ if (safe_to_lower || watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns ++ > hubbub1->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns) { ++ hubbub1->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = ++ watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns; ++ prog_wm_value = convert_and_clamp( ++ watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, ++ refclk_mhz, 0x1fffff); ++ REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0, ++ DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value, ++ DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value); ++ DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_C calculated =%d\n" ++ "HW register value = 0x%x\n", ++ watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); ++ } ++ ++ if (safe_to_lower || watermarks->c.cstate_pstate.cstate_exit_ns ++ > hubbub1->watermarks.c.cstate_pstate.cstate_exit_ns) { ++ hubbub1->watermarks.c.cstate_pstate.cstate_exit_ns = ++ watermarks->c.cstate_pstate.cstate_exit_ns; ++ prog_wm_value = convert_and_clamp( ++ watermarks->c.cstate_pstate.cstate_exit_ns, ++ refclk_mhz, 0x1fffff); ++ REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0, ++ DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value, ++ DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value); ++ DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_C calculated =%d\n" ++ "HW register value = 0x%x\n", ++ watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value); ++ } ++ ++ /* clock state D */ ++ if (safe_to_lower || watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns ++ > hubbub1->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns) { ++ hubbub1->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = ++ watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns; ++ prog_wm_value = convert_and_clamp( ++ watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, ++ refclk_mhz, 0x1fffff); ++ REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, 0, ++ DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value, ++ DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value); ++ DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_D calculated =%d\n" ++ "HW register value = 0x%x\n", ++ watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); ++ } ++ ++ if (safe_to_lower || watermarks->d.cstate_pstate.cstate_exit_ns ++ > hubbub1->watermarks.d.cstate_pstate.cstate_exit_ns) { ++ hubbub1->watermarks.d.cstate_pstate.cstate_exit_ns = ++ watermarks->d.cstate_pstate.cstate_exit_ns; ++ prog_wm_value = convert_and_clamp( ++ watermarks->d.cstate_pstate.cstate_exit_ns, ++ refclk_mhz, 0x1fffff); ++ REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, 0, ++ DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value, ++ DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value); ++ DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_D calculated =%d\n" ++ "HW register value = 0x%x\n", ++ watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value); ++ } ++} ++ ++static void hubbub21_program_pstate_watermarks( ++ struct hubbub *hubbub, ++ struct dcn_watermark_set *watermarks, ++ unsigned int refclk_mhz, ++ bool safe_to_lower) ++{ ++ struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); ++ uint32_t prog_wm_value; ++ ++ /* clock state A */ ++ if (safe_to_lower || watermarks->a.cstate_pstate.pstate_change_ns ++ > hubbub1->watermarks.a.cstate_pstate.pstate_change_ns) { ++ hubbub1->watermarks.a.cstate_pstate.pstate_change_ns = ++ watermarks->a.cstate_pstate.pstate_change_ns; ++ prog_wm_value = convert_and_clamp( ++ watermarks->a.cstate_pstate.pstate_change_ns, ++ refclk_mhz, 0x1fffff); ++ REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, 0, ++ DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value, ++ DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value); ++ DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n" ++ "HW register value = 0x%x\n\n", ++ watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value); ++ } ++ ++ /* clock state B */ ++ if (safe_to_lower || watermarks->b.cstate_pstate.pstate_change_ns ++ > hubbub1->watermarks.b.cstate_pstate.pstate_change_ns) { ++ hubbub1->watermarks.b.cstate_pstate.pstate_change_ns = ++ watermarks->b.cstate_pstate.pstate_change_ns; ++ prog_wm_value = convert_and_clamp( ++ watermarks->b.cstate_pstate.pstate_change_ns, ++ refclk_mhz, 0x1fffff); ++ REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, 0, ++ DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value, ++ DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value); ++ DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n" ++ "HW register value = 0x%x\n\n", ++ watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value); ++ } ++ ++ /* clock state C */ ++ if (safe_to_lower || watermarks->c.cstate_pstate.pstate_change_ns ++ > hubbub1->watermarks.c.cstate_pstate.pstate_change_ns) { ++ hubbub1->watermarks.c.cstate_pstate.pstate_change_ns = ++ watermarks->c.cstate_pstate.pstate_change_ns; ++ prog_wm_value = convert_and_clamp( ++ watermarks->c.cstate_pstate.pstate_change_ns, ++ refclk_mhz, 0x1fffff); ++ REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, 0, ++ DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value, ++ DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value); ++ DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n" ++ "HW register value = 0x%x\n\n", ++ watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value); ++ } ++ ++ /* clock state D */ ++ if (safe_to_lower || watermarks->d.cstate_pstate.pstate_change_ns ++ > hubbub1->watermarks.d.cstate_pstate.pstate_change_ns) { ++ hubbub1->watermarks.d.cstate_pstate.pstate_change_ns = ++ watermarks->d.cstate_pstate.pstate_change_ns; ++ prog_wm_value = convert_and_clamp( ++ watermarks->d.cstate_pstate.pstate_change_ns, ++ refclk_mhz, 0x1fffff); ++ REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, 0, ++ DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value, ++ DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value); ++ DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n" ++ "HW register value = 0x%x\n\n", ++ watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value); ++ } ++} ++ ++void hubbub21_program_watermarks( ++ struct hubbub *hubbub, ++ struct dcn_watermark_set *watermarks, ++ unsigned int refclk_mhz, ++ bool safe_to_lower) ++{ ++ struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); ++ ++ hubbub21_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower); ++ hubbub21_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower); ++ hubbub21_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower); ++ ++ /* ++ * The DCHub arbiter has a mechanism to dynamically rate limit the DCHub request stream to the fabric. ++ * If the memory controller is fully utilized and the DCHub requestors are ++ * well ahead of their amortized schedule, then it is safe to prevent the next winner ++ * from being committed and sent to the fabric. ++ * The utilization of the memory controller is approximated by ensuring that ++ * the number of outstanding requests is greater than a threshold specified ++ * by the ARB_MIN_REQ_OUTSTANDING. To determine that the DCHub requestors are well ahead of the amortized schedule, ++ * the slack of the next winner is compared with the ARB_SAT_LEVEL in DLG RefClk cycles. ++ * ++ * TODO: Revisit request limit after figure out right number. request limit for Renoir isn't decided yet, set maximum value (0x1FF) ++ * to turn off it for now. ++ */ ++ REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0, ++ DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz); ++ REG_UPDATE_2(DCHUBBUB_ARB_DF_REQ_OUTSTAND, ++ DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF, ++ DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, 0xA); ++ REG_UPDATE(DCHUBBUB_ARB_HOSTVM_CNTL, ++ DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD, 0xF); ++ ++ hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter); ++} ++ ++void hubbub21_wm_read_state(struct hubbub *hubbub, ++ struct dcn_hubbub_wm *wm) ++{ ++ struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); ++ struct dcn_hubbub_wm_set *s; ++ ++ memset(wm, 0, sizeof(struct dcn_hubbub_wm)); ++ ++ s = &wm->sets[0]; ++ s->wm_set = 0; ++ REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, ++ DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, &s->data_urgent); ++ ++ REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, ++ DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, &s->sr_enter); ++ ++ REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, ++ DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, &s->sr_exit); ++ ++ REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, ++ DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, &s->dram_clk_chanage); ++ ++ s = &wm->sets[1]; ++ s->wm_set = 1; ++ REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, ++ DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, &s->data_urgent); ++ ++ REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, ++ DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, &s->sr_enter); ++ ++ REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, ++ DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, &s->sr_exit); ++ ++ REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, ++ DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, &s->dram_clk_chanage); ++ ++ s = &wm->sets[2]; ++ s->wm_set = 2; ++ REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, ++ DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, &s->data_urgent); ++ ++ REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, ++ DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, &s->sr_enter); ++ ++ REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, ++ DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, &s->sr_exit); ++ ++ REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, ++ DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, &s->dram_clk_chanage); ++ ++ s = &wm->sets[3]; ++ s->wm_set = 3; ++ REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, ++ DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, &s->data_urgent); ++ ++ REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, ++ DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, &s->sr_enter); ++ ++ REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, ++ DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, &s->sr_exit); ++ ++ REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, ++ DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, &s->dram_clk_chanage); ++} ++ ++ ++static const struct hubbub_funcs hubbub21_funcs = { ++ .update_dchub = hubbub2_update_dchub, ++ .init_dchub_sys_ctx = hubbub21_init_dchub, ++ .init_vm_ctx = NULL, ++ .dcc_support_swizzle = hubbub2_dcc_support_swizzle, ++ .dcc_support_pixel_format = hubbub2_dcc_support_pixel_format, ++ .get_dcc_compression_cap = hubbub2_get_dcc_compression_cap, ++ .wm_read_state = hubbub21_wm_read_state, ++ .get_dchub_ref_freq = hubbub2_get_dchub_ref_freq, ++ .program_watermarks = hubbub21_program_watermarks, ++}; ++ ++void hubbub21_construct(struct dcn20_hubbub *hubbub, ++ struct dc_context *ctx, ++ const struct dcn_hubbub_registers *hubbub_regs, ++ const struct dcn_hubbub_shift *hubbub_shift, ++ const struct dcn_hubbub_mask *hubbub_mask) ++{ ++ hubbub->base.ctx = ctx; ++ ++ hubbub->base.funcs = &hubbub21_funcs; ++ ++ hubbub->regs = hubbub_regs; ++ hubbub->shifts = hubbub_shift; ++ hubbub->masks = hubbub_mask; ++ ++ hubbub->debug_test_index_pstate = 0xB; ++} +diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h +new file mode 100644 +index 000000000000..6ff3cdb89178 +--- /dev/null ++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h +@@ -0,0 +1,132 @@ ++/* ++* Copyright 2018 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: AMD ++ * ++ */ ++#ifndef DAL_DC_DCN21_DCN21_HUBBUB_H_ ++#define DAL_DC_DCN21_DCN21_HUBBUB_H_ ++ ++#include "dcn20/dcn20_hubbub.h" ++ ++#define HUBBUB_HVM_REG_LIST() \ ++ SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\ ++ SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\ ++ SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\ ++ SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\ ++ SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\ ++ SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\ ++ SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\ ++ SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\ ++ SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ ++ SR(DCHVM_CTRL0), \ ++ SR(DCHVM_MEM_CTRL), \ ++ SR(DCHVM_CLK_CTRL), \ ++ SR(DCHVM_RIOMMU_CTRL0), \ ++ SR(DCHVM_RIOMMU_STAT0) ++ ++#define HUBBUB_REG_LIST_DCN21()\ ++ HUBBUB_REG_LIST_DCN_COMMON(), \ ++ HUBBUB_SR_WATERMARK_REG_LIST(), \ ++ HUBBUB_HVM_REG_LIST(), \ ++ SR(DCHUBBUB_CRC_CTRL), \ ++ SR(DCN_VM_FB_LOCATION_BASE),\ ++ SR(DCN_VM_FB_LOCATION_TOP),\ ++ SR(DCN_VM_FB_OFFSET),\ ++ SR(DCN_VM_AGP_BOT),\ ++ SR(DCN_VM_AGP_TOP),\ ++ SR(DCN_VM_AGP_BASE) ++ ++#define HUBBUB_MASK_SH_LIST_HVM(mask_sh) \ ++ HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, mask_sh), \ ++ HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, mask_sh), \ ++ HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, mask_sh), \ ++ HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, mask_sh), \ ++ HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, mask_sh), \ ++ HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, mask_sh), \ ++ HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, mask_sh), \ ++ HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, mask_sh), \ ++ HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, mask_sh), \ ++ HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A, mask_sh), \ ++ HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B, mask_sh), \ ++ HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C, mask_sh), \ ++ HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D, mask_sh), \ ++ HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A, mask_sh), \ ++ HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B, mask_sh), \ ++ HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C, mask_sh), \ ++ HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D, mask_sh), \ ++ HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, mask_sh), \ ++ HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B, mask_sh), \ ++ HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C, mask_sh), \ ++ HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D, mask_sh), \ ++ HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, mask_sh), \ ++ HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, mask_sh), \ ++ HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, mask_sh), \ ++ HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, mask_sh), \ ++ HUBBUB_SF(DCHUBBUB_ARB_HOSTVM_CNTL, DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD, mask_sh), \ ++ HUBBUB_SF(DCHVM_CTRL0, HOSTVM_INIT_REQ, mask_sh), \ ++ HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_PWR_REQ_DIS, mask_sh), \ ++ HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_FORCE_REQ, mask_sh), \ ++ HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_POWER_STATUS, mask_sh), \ ++ HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_R_GATE_DIS, mask_sh), \ ++ HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_G_GATE_DIS, mask_sh), \ ++ HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_R_GATE_DIS, mask_sh), \ ++ HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_G_GATE_DIS, mask_sh), \ ++ HUBBUB_SF(DCHVM_CLK_CTRL, TR_REQ_REQCLKREQ_MODE, mask_sh), \ ++ HUBBUB_SF(DCHVM_CLK_CTRL, TW_RSP_COMPCLKREQ_MODE, mask_sh), \ ++ HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, mask_sh), \ ++ HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, mask_sh), \ ++ HUBBUB_SF(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, mask_sh), \ ++ HUBBUB_SF(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, mask_sh), \ ++ HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, mask_sh), \ ++ HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, mask_sh), \ ++ HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, mask_sh), \ ++ HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, mask_sh) ++ ++#define HUBBUB_MASK_SH_LIST_DCN21(mask_sh)\ ++ HUBBUB_MASK_SH_LIST_HVM(mask_sh),\ ++ HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \ ++ HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \ ++ HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ ++ HUBBUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE, mask_sh), \ ++ HUBBUB_SF(DCN_VM_FB_LOCATION_TOP, FB_TOP, mask_sh), \ ++ HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \ ++ HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \ ++ HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \ ++ HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh) ++ ++void dcn21_dchvm_init(struct hubbub *hubbub); ++void hubbub21_program_watermarks( ++ struct hubbub *hubbub, ++ struct dcn_watermark_set *watermarks, ++ unsigned int refclk_mhz, ++ bool safe_to_lower); ++ ++void hubbub21_wm_read_state(struct hubbub *hubbub, ++ struct dcn_hubbub_wm *wm); ++ ++void hubbub21_construct(struct dcn20_hubbub *hubbub, ++ struct dc_context *ctx, ++ const struct dcn_hubbub_registers *hubbub_regs, ++ const struct dcn_hubbub_shift *hubbub_shift, ++ const struct dcn_hubbub_mask *hubbub_mask); ++ ++#endif /* DAL_DC_DCN21_DCN21_HUBBUB_H_ */ +-- +2.17.1 + |