diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3634-drm-amd-display-Add-pp_smu-functions-for-Renoir.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3634-drm-amd-display-Add-pp_smu-functions-for-Renoir.patch | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3634-drm-amd-display-Add-pp_smu-functions-for-Renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3634-drm-amd-display-Add-pp_smu-functions-for-Renoir.patch new file mode 100644 index 00000000..e2c2d7ee --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3634-drm-amd-display-Add-pp_smu-functions-for-Renoir.patch @@ -0,0 +1,90 @@ +From d354716729becd3e83a6b15119ac73badd8c7fac Mon Sep 17 00:00:00 2001 +From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Date: Thu, 25 Jul 2019 15:58:18 -0400 +Subject: [PATCH 3634/4256] drm/amd/display: Add pp_smu functions for Renoir + +This defines the interface for communicating requirements +between DC and powerplay. + +Acked-by: Harry Wentland <harry.wentland@amd.com> +Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 47 ++++++++++++++++++++++ + 1 file changed, 47 insertions(+) + +diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h +index 825e097e4bab..6aa1686f59ab 100644 +--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h ++++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h +@@ -44,6 +44,9 @@ enum pp_smu_ver { + #ifndef CONFIG_TRIM_DRM_AMD_DC_DCN2_0 + PP_SMU_VER_NV, + #endif ++#if defined(CONFIG_DRM_AMD_DC_DCN2_1) ++ PP_SMU_VER_RN, ++#endif + + PP_SMU_VER_MAX + }; +@@ -240,6 +243,47 @@ struct pp_smu_funcs_nv { + }; + #endif + ++#if defined(CONFIG_DRM_AMD_DC_DCN2_1) ++ ++#define PP_SMU_NUM_SOCCLK_DPM_LEVELS 8 ++#define PP_SMU_NUM_DCFCLK_DPM_LEVELS 4 ++#define PP_SMU_NUM_FCLK_DPM_LEVELS 4 ++#define PP_SMU_NUM_MEMCLK_DPM_LEVELS 4 ++ ++struct dpm_clock { ++ uint32_t Freq; // In MHz ++ uint32_t Vol; // Millivolts with 2 fractional bits ++}; ++ ++ ++/* this is a copy of the structure defined in smuxx_driver_if.h*/ ++struct dpm_clocks { ++ struct dpm_clock DcfClocks[PP_SMU_NUM_DCFCLK_DPM_LEVELS]; ++ struct dpm_clock SocClocks[PP_SMU_NUM_SOCCLK_DPM_LEVELS]; ++ struct dpm_clock FClocks[PP_SMU_NUM_FCLK_DPM_LEVELS]; ++ struct dpm_clock MemClocks[PP_SMU_NUM_MEMCLK_DPM_LEVELS]; ++}; ++ ++ ++struct pp_smu_funcs_rn { ++ struct pp_smu pp_smu; ++ ++ /* ++ * reader and writer WM's are sent together as part of one table ++ * ++ * PPSMC_MSG_SetDriverDramAddrHigh ++ * PPSMC_MSG_SetDriverDramAddrLow ++ * PPSMC_MSG_TransferTableDram2Smu ++ * ++ */ ++ enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp, ++ struct pp_smu_wm_range_sets *ranges); ++ ++ enum pp_smu_status (*get_dpm_clock_table) (struct pp_smu *pp, ++ struct dpm_clocks *clock_table); ++}; ++#endif ++ + struct pp_smu_funcs { + struct pp_smu ctx; + union { +@@ -247,6 +291,9 @@ struct pp_smu_funcs { + #ifndef CONFIG_TRIM_DRM_AMD_DC_DCN2_0 + struct pp_smu_funcs_nv nv_funcs; + #endif ++#if defined(CONFIG_DRM_AMD_DC_DCN2_1) ++ struct pp_smu_funcs_rn rn_funcs; ++#endif + + }; + }; +-- +2.17.1 + |