diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3632-drm-amd-display-Add-Renoir-clock-registers-list.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3632-drm-amd-display-Add-Renoir-clock-registers-list.patch | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3632-drm-amd-display-Add-Renoir-clock-registers-list.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3632-drm-amd-display-Add-Renoir-clock-registers-list.patch new file mode 100644 index 00000000..cd579fbb --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3632-drm-amd-display-Add-Renoir-clock-registers-list.patch @@ -0,0 +1,45 @@ +From 361fe908a646059f025ac00c83c7c59bdd187c84 Mon Sep 17 00:00:00 2001 +From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Date: Thu, 25 Jul 2019 15:51:09 -0400 +Subject: [PATCH 3632/4256] drm/amd/display: Add Renoir clock registers list + +These are the registers used to program the clock hw. + +Acked-by: Harry Wentland <harry.wentland@amd.com> +Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../drm/amd/display/dc/dce/dce_clock_source.h | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h +index adae03b1f3a7..43c1bf60b83c 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h +@@ -78,6 +78,23 @@ + SRII(PIXEL_RATE_CNTL, OTG, 5) + #endif + ++#if defined(CONFIG_DRM_AMD_DC_DCN2_1) ++#define CS_COMMON_REG_LIST_DCN2_1(index, pllid) \ ++ SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ ++ SRII(PHASE, DP_DTO, 0),\ ++ SRII(PHASE, DP_DTO, 1),\ ++ SRII(PHASE, DP_DTO, 2),\ ++ SRII(PHASE, DP_DTO, 3),\ ++ SRII(MODULO, DP_DTO, 0),\ ++ SRII(MODULO, DP_DTO, 1),\ ++ SRII(MODULO, DP_DTO, 2),\ ++ SRII(MODULO, DP_DTO, 3),\ ++ SRII(PIXEL_RATE_CNTL, OTG, 0),\ ++ SRII(PIXEL_RATE_CNTL, OTG, 1),\ ++ SRII(PIXEL_RATE_CNTL, OTG, 2),\ ++ SRII(PIXEL_RATE_CNTL, OTG, 3) ++#endif ++ + #if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\ + CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\ +-- +2.17.1 + |