diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3597-drm-amd-display-flicking-observed-while-installing-d.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3597-drm-amd-display-flicking-observed-while-installing-d.patch | 106 |
1 files changed, 106 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3597-drm-amd-display-flicking-observed-while-installing-d.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3597-drm-amd-display-flicking-observed-while-installing-d.patch new file mode 100644 index 00000000..b19cc9de --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3597-drm-amd-display-flicking-observed-while-installing-d.patch @@ -0,0 +1,106 @@ +From 7dd9326342944b266c07c1abcdabb4e01a5a3fd8 Mon Sep 17 00:00:00 2001 +From: hersen wu <hersenxs.wu@amd.com> +Date: Fri, 2 Aug 2019 16:01:37 -0400 +Subject: [PATCH 3597/4256] drm/amd/display: flicking observed while installing + driver on Navi10 CF + +[WHY] value of dchub_ref_clock is decided by dchubbub global timer +settings which is programmed by vbios command table disp_init. +for multi-GPU case, vbios is posted only for primary GPU. without +vbios posted for the secondary GPU, value of dchub_ref_clock is not +set properly. this value will affect dcn bandwidth calcuation and +cause underflow. user will see screen flicking during driver +installation for dual GPU case. + +[HOW] dc init_hw always call vbios command table disp_init to +make sure dchubbub global timer is configured and enable. + +Signed-off-by: hersen wu <hersenxs.wu@amd.com> +Reviewed-by: Jun Lei <Jun.Lei@amd.com> +Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +--- + .../gpu/drm/amd/display/dc/core/dc_resource.c | 1 + + .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 54 +++++++++---------- + 2 files changed, 28 insertions(+), 27 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +index 6e88cb0fffce..adbf2d4e1723 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +@@ -169,6 +169,7 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc, + default: + break; + } ++ + if (res_pool != NULL) { + if (dc->ctx->dc_bios->fw_info_valid) { + res_pool->ref_clocks.xtalin_clock_inKhz = +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index b981ea849cc9..866705ea45a7 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -1208,34 +1208,34 @@ static void dcn10_init_hw(struct dc *dc) + return; + } + +- if (!dcb->funcs->is_accelerated_mode(dcb)) { +- dc->hwss.bios_golden_init(dc); +- if (dc->ctx->dc_bios->fw_info_valid) { +- res_pool->ref_clocks.xtalin_clock_inKhz = +- dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; +- +- if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { +- if (res_pool->dccg && res_pool->hubbub) { +- +- (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, +- dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, +- &res_pool->ref_clocks.dccg_ref_clock_inKhz); +- +- (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, +- res_pool->ref_clocks.dccg_ref_clock_inKhz, +- &res_pool->ref_clocks.dchub_ref_clock_inKhz); +- } else { +- // Not all ASICs have DCCG sw component +- res_pool->ref_clocks.dccg_ref_clock_inKhz = +- res_pool->ref_clocks.xtalin_clock_inKhz; +- res_pool->ref_clocks.dchub_ref_clock_inKhz = +- res_pool->ref_clocks.xtalin_clock_inKhz; +- } +- } +- } else +- ASSERT_CRITICAL(false); ++ if (!dcb->funcs->is_accelerated_mode(dcb)) + dc->hwss.disable_vga(dc->hwseq); +- } ++ ++ dc->hwss.bios_golden_init(dc); ++ if (dc->ctx->dc_bios->fw_info_valid) { ++ res_pool->ref_clocks.xtalin_clock_inKhz = ++ dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; ++ ++ if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { ++ if (res_pool->dccg && res_pool->hubbub) { ++ ++ (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, ++ dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, ++ &res_pool->ref_clocks.dccg_ref_clock_inKhz); ++ ++ (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, ++ res_pool->ref_clocks.dccg_ref_clock_inKhz, ++ &res_pool->ref_clocks.dchub_ref_clock_inKhz); ++ } else { ++ // Not all ASICs have DCCG sw component ++ res_pool->ref_clocks.dccg_ref_clock_inKhz = ++ res_pool->ref_clocks.xtalin_clock_inKhz; ++ res_pool->ref_clocks.dchub_ref_clock_inKhz = ++ res_pool->ref_clocks.xtalin_clock_inKhz; ++ } ++ } ++ } else ++ ASSERT_CRITICAL(false); + + for (i = 0; i < dc->link_count; i++) { + /* Power up AND update implementation according to the +-- +2.17.1 + |