diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3596-drm-amd-display-Properly-read-LVTMA_PWRSEQ_CNTL.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3596-drm-amd-display-Properly-read-LVTMA_PWRSEQ_CNTL.patch | 131 |
1 files changed, 131 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3596-drm-amd-display-Properly-read-LVTMA_PWRSEQ_CNTL.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3596-drm-amd-display-Properly-read-LVTMA_PWRSEQ_CNTL.patch new file mode 100644 index 00000000..ae6a02d1 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3596-drm-amd-display-Properly-read-LVTMA_PWRSEQ_CNTL.patch @@ -0,0 +1,131 @@ +From b2fd66dbcd4221d74390739688d35cb2cfb03ee9 Mon Sep 17 00:00:00 2001 +From: Joshua Aberback <joshua.aberback@amd.com> +Date: Thu, 8 Aug 2019 13:22:36 -0400 +Subject: [PATCH 3596/4256] drm/amd/display: Properly read LVTMA_PWRSEQ_CNTL + +[Why] +The register LVTMA_PWRSEQ_CNTL is used to determine the power state of the +embedded display. Currently we do not actually read this register's values, +so during power down we think that this display is already off, so we skip +calling into VBIOS to actually turn it off. + +[How] + - add relevant fields to shift / mask initialization + +Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> +Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> +Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +--- + .../gpu/drm/amd/display/dc/dce/dce_hwseq.h | 43 ++++++++----------- + 1 file changed, 17 insertions(+), 26 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +index f62eb2e43d7f..7d93babaa2fb 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +@@ -416,36 +416,34 @@ struct dce_hwseq_registers { + HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\ + HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh) + ++#define HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)\ ++ HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ ++ HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh),\ ++ HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh),\ ++ HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) ++ + #define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\ + .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \ + HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ + HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ + HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ + HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\ +- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ +- HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\ +- HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) ++ HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ ++ HWSEQ_LVTMA_MASK_SH_LIST(mask_sh) + + #define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\ + HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\ + HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\ +- HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_), \ +- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ +- HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) ++ HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ ++ HWSEQ_LVTMA_MASK_SH_LIST(mask_sh) + + #define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\ + HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ + SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\ +- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ +- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh),\ +- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh),\ +- HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\ + HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) + + #define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\ + HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ +- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ +- HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\ + HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) + + #define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\ +@@ -453,18 +451,15 @@ struct dce_hwseq_registers { + SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\ + SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\ + SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\ +- SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh), \ +- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ +- HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) ++ SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh) + + #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\ + HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\ + HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\ + HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ + HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\ +- HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh), \ +- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ +- HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) ++ HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh),\ ++ HWSEQ_LVTMA_MASK_SH_LIST(mask_sh) + + #define HWSEQ_VG20_MASK_SH_LIST(mask_sh)\ + HWSEQ_DCE12_MASK_SH_LIST(mask_sh),\ +@@ -527,10 +522,7 @@ struct dce_hwseq_registers { + HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\ + HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\ + HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\ +- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ +- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh), \ +- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh), \ +- HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) ++ HWSEQ_LVTMA_MASK_SH_LIST(mask_sh) + + #if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #define HWSEQ_DCN2_MASK_SH_LIST(mask_sh)\ +@@ -591,8 +583,7 @@ struct dce_hwseq_registers { + HWS_SF(, DOMAIN20_PG_STATUS, DOMAIN20_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN21_PG_STATUS, DOMAIN21_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ +- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ +- HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) ++ HWSEQ_LVTMA_MASK_SH_LIST(mask_sh) + #endif + + #define HWSEQ_REG_FIELD_LIST(type) \ +@@ -627,9 +618,9 @@ struct dce_hwseq_registers { + type ENABLE_L1_TLB;\ + type SYSTEM_ACCESS_MODE;\ + type LVTMA_BLON;\ +- type LVTMA_PWRSEQ_TARGET_STATE_R;\ + type LVTMA_DIGON;\ +- type LVTMA_DIGON_OVRD; ++ type LVTMA_DIGON_OVRD;\ ++ type LVTMA_PWRSEQ_TARGET_STATE_R; + + #define HWSEQ_DCN_REG_FIELD_LIST(type) \ + type HUBP_VTG_SEL; \ +-- +2.17.1 + |