aboutsummaryrefslogtreecommitdiffstats
path: root/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3593-drm-amd-display-Expose-OTG_V_TOTAL_MID-for-HW-Diags.patch
diff options
context:
space:
mode:
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3593-drm-amd-display-Expose-OTG_V_TOTAL_MID-for-HW-Diags.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3593-drm-amd-display-Expose-OTG_V_TOTAL_MID-for-HW-Diags.patch213
1 files changed, 213 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3593-drm-amd-display-Expose-OTG_V_TOTAL_MID-for-HW-Diags.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3593-drm-amd-display-Expose-OTG_V_TOTAL_MID-for-HW-Diags.patch
new file mode 100644
index 00000000..4869f02f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3593-drm-amd-display-Expose-OTG_V_TOTAL_MID-for-HW-Diags.patch
@@ -0,0 +1,213 @@
+From 9e58c1d3b340644693597dd1a91ef3616f109f27 Mon Sep 17 00:00:00 2001
+From: Bayan Zabihiyan <bayan.zabihiyan@amd.com>
+Date: Thu, 8 Aug 2019 11:08:52 -0400
+Subject: [PATCH 3593/4256] drm/amd/display: Expose OTG_V_TOTAL_MID for HW
+ Diags
+
+[Why]
+Existing HW Features, HW Diags test requested that the
+registers be exposed.
+
+[How]
+Add V_TOTAL_MID to existing DC structures.
+Make sure values are passed down throughout DC
+Add Register definition.
+Program the additional registers
+Add additional Logic for V_TOTAL_CONTROL.
+
+Signed-off-by: Bayan Zabihiyan <bayan.zabihiyan@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +++-
+ drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 ++
+ .../drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 3 ++-
+ .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 5 ++++-
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 12 ++++++++++++
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 8 ++++++++
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2 ++
+ .../gpu/drm/amd/display/dc/inc/hw/timing_generator.h | 2 ++
+ drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 3 ++-
+ 9 files changed, 37 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index bae845dfd069..8dd9db41bc4a 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -294,7 +294,9 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,
+ dc->hwss.set_drr(&pipe,
+ 1,
+ adjust->v_total_min,
+- adjust->v_total_max);
++ adjust->v_total_max,
++ adjust->v_total_mid,
++ adjust->v_total_mid_frame_num);
+
+ ret = true;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+index f35826d5d1e5..0b8700a8a94a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+@@ -757,6 +757,8 @@ struct crtc_trigger_info {
+ struct dc_crtc_timing_adjust {
+ uint32_t v_total_min;
+ uint32_t v_total_max;
++ uint32_t v_total_mid;
++ uint32_t v_total_mid_frame_num;
+ };
+
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index c2d026ba269f..c273490ddcab 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -1716,7 +1716,8 @@ void dce110_set_safe_displaymarks(
+ ******************************************************************************/
+
+ static void set_drr(struct pipe_ctx **pipe_ctx,
+- int num_pipes, int vmin, int vmax)
++ int num_pipes, unsigned int vmin, unsigned int vmax,
++ unsigned int vmid, unsigned int vmid_frame_number)
+ {
+ int i = 0;
+ struct drr_params params = {0};
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 5057a8946a71..b981ea849cc9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -2745,7 +2745,8 @@ static void dcn10_optimize_bandwidth(
+ }
+
+ static void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
+- int num_pipes, int vmin, int vmax)
++ int num_pipes, unsigned int vmin, unsigned int vmax,
++ unsigned int vmid, unsigned int vmid_frame_number)
+ {
+ int i = 0;
+ struct drr_params params = {0};
+@@ -2754,6 +2755,8 @@ static void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
+
+ params.vertical_total_max = vmax;
+ params.vertical_total_min = vmin;
++ params.vertical_total_mid = vmid;
++ params.vertical_total_mid_frame_num = vmid_frame_number;
+
+ /* TODO: If multiple pipes are to be supported, you need
+ * some GSL stuff. Static screen triggers may be programmed differently
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+index 66d8f6410b53..f3cade20e45c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+@@ -858,6 +858,18 @@ void optc1_set_drr(
+ params->vertical_total_max > 0 &&
+ params->vertical_total_min > 0) {
+
++ if (params->vertical_total_mid != 0) {
++
++ REG_SET(OTG_V_TOTAL_MID, 0,
++ OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
++
++ REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
++ OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
++ OTG_VTOTAL_MID_FRAME_NUM,
++ (uint8_t)params->vertical_total_mid_frame_num);
++
++ }
++
+ REG_SET(OTG_V_TOTAL_MAX, 0,
+ OTG_V_TOTAL_MAX, params->vertical_total_max - 1);
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+index 82d91ab54ba5..83575599672e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+@@ -54,6 +54,7 @@
+ SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
+ SRI(OTG_STEREO_STATUS, OTG, inst),\
+ SRI(OTG_V_TOTAL_MAX, OTG, inst),\
++ SRI(OTG_V_TOTAL_MID, OTG, inst),\
+ SRI(OTG_V_TOTAL_MIN, OTG, inst),\
+ SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
+ SRI(OTG_TRIGA_CNTL, OTG, inst),\
+@@ -125,6 +126,7 @@ struct dcn_optc_registers {
+ uint32_t OTG_3D_STRUCTURE_CONTROL;
+ uint32_t OTG_STEREO_STATUS;
+ uint32_t OTG_V_TOTAL_MAX;
++ uint32_t OTG_V_TOTAL_MID;
+ uint32_t OTG_V_TOTAL_MIN;
+ uint32_t OTG_V_TOTAL_CONTROL;
+ uint32_t OTG_TRIGA_CNTL;
+@@ -214,12 +216,15 @@ struct dcn_optc_registers {
+ SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
+ SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
+ SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
++ SF(OTG0_OTG_V_TOTAL_MID, OTG_V_TOTAL_MID, mask_sh),\
+ SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
+ SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
+ SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
+ SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
+ SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK_EN, mask_sh),\
+ SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
++ SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
++ SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_FRAME_NUM, mask_sh),\
+ SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
+ SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
+ SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
+@@ -348,9 +353,12 @@ struct dcn_optc_registers {
+ type OTG_3D_STRUCTURE_V_UPDATE_MODE;\
+ type OTG_3D_STRUCTURE_STEREO_SEL_OVR;\
+ type OTG_V_TOTAL_MAX;\
++ type OTG_V_TOTAL_MID;\
+ type OTG_V_TOTAL_MIN;\
+ type OTG_V_TOTAL_MIN_SEL;\
+ type OTG_V_TOTAL_MAX_SEL;\
++ type OTG_VTOTAL_MID_REPLACING_MAX_EN;\
++ type OTG_VTOTAL_MID_FRAME_NUM;\
+ type OTG_FORCE_LOCK_ON_EVENT;\
+ type OTG_SET_V_TOTAL_MIN_MASK_EN;\
+ type OTG_SET_V_TOTAL_MIN_MASK;\
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 230a4216c2ae..adad15eb5d12 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -597,6 +597,8 @@ enum dc_status dcn20_enable_stream_timing(
+
+ params.vertical_total_min = stream->adjust.v_total_min;
+ params.vertical_total_max = stream->adjust.v_total_max;
++ params.vertical_total_mid = stream->adjust.v_total_mid;
++ params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num;
+ if (pipe_ctx->stream_res.tg->funcs->set_drr)
+ pipe_ctx->stream_res.tg->funcs->set_drr(
+ pipe_ctx->stream_res.tg, &params);
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+index e0713d6d6c8d..6196cc32356e 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+@@ -59,6 +59,8 @@ struct gsl_params {
+ struct drr_params {
+ uint32_t vertical_total_min;
+ uint32_t vertical_total_max;
++ uint32_t vertical_total_mid;
++ uint32_t vertical_total_mid_frame_num;
+ bool immediate_flip;
+ };
+
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+index 68b1185f0636..732a93df1844 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+@@ -237,7 +237,8 @@ struct hw_sequencer_funcs {
+ #endif
+
+ void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
+- int vmin, int vmax);
++ unsigned int vmin, unsigned int vmax,
++ unsigned int vmid, unsigned int vmid_frame_number);
+
+ void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,
+ struct crtc_position *position);
+--
+2.17.1
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-18 03:19:40 +0000