diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3573-drm-amd-display-Zero-out-dsc-init-regs.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3573-drm-amd-display-Zero-out-dsc-init-regs.patch | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3573-drm-amd-display-Zero-out-dsc-init-regs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3573-drm-amd-display-Zero-out-dsc-init-regs.patch new file mode 100644 index 00000000..cfc419bd --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3573-drm-amd-display-Zero-out-dsc-init-regs.patch @@ -0,0 +1,46 @@ +From aae213cf382fa9a3cf10f708ac18d6cb08f5f50d Mon Sep 17 00:00:00 2001 +From: Nikola Cornij <nikola.cornij@amd.com> +Date: Thu, 1 Aug 2019 15:52:58 -0400 +Subject: [PATCH 3573/4256] drm/amd/display: Zero-out dsc init regs + +[why] +Before a statically allocated PPS data structure, that did +get zeroed-out at startup, had been re-used for making packed PPS +SDP. With S3 fix, using a non-initialized PPS data structure was +introduced, while wrongly assuming it'd get initialized before it's +populated. As a consequence 'vbr_enable' and perhaps some other +fields are left uninitialized when making packed PPS SDP. This can +affect 'simple_422' as well because of the way PPS SDP packing is +done (the fields are not masked first, only shifted). The behavior +will be different, depending on the content of uninitialized data. + +[how] +Zero-out PPS data structure at initialization time before it's +populated + +Fixes: 3b87378c604e929015385e5cc76d0bbd55c05347 + drm/amd/display: Set DSC before DIG front-end is connected to its back-end + +Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> +Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> +Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c +index 379c9e4ac63b..c4f861e6bd53 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c +@@ -447,6 +447,8 @@ static void dsc_init_reg_values(struct dsc_reg_values *reg_vals) + { + int i; + ++ memset(reg_vals, 0, sizeof(struct dsc_reg_values)); ++ + /* Non-PPS values */ + reg_vals->dsc_clock_enable = 1; + reg_vals->dsc_clock_gating_disable = 0; +-- +2.17.1 + |