diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3551-drm-amd-display-Add-PIXEL_RATE-control-regs-for-more.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3551-drm-amd-display-Add-PIXEL_RATE-control-regs-for-more.patch | 79 |
1 files changed, 79 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3551-drm-amd-display-Add-PIXEL_RATE-control-regs-for-more.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3551-drm-amd-display-Add-PIXEL_RATE-control-regs-for-more.patch new file mode 100644 index 00000000..b2616465 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3551-drm-amd-display-Add-PIXEL_RATE-control-regs-for-more.patch @@ -0,0 +1,79 @@ +From a8ff8f2b90598b4ab827dc8d35703c5d03869499 Mon Sep 17 00:00:00 2001 +From: Yongqiang Sun <yongqiang.sun@amd.com> +Date: Sat, 22 Jun 2019 18:52:41 -0400 +Subject: [PATCH 3551/4256] drm/amd/display: Add PIXEL_RATE control regs for + more instances + +For use by future ASICs + +(cherry picked from commit 08a026f1ae782884b18dfa108de019a5a985e92a) +Signed-off-by: Sung Lee <sung.lee@amd.com> +Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> +Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +--- + .../gpu/drm/amd/display/dc/dce/dce_hwseq.h | 25 +++++++++++++++---- + 1 file changed, 20 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +index 245b80b92681..f62eb2e43d7f 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +@@ -62,6 +62,10 @@ + SRII(BLND_CONTROL, BLND, 4), \ + SRII(BLND_CONTROL, BLND, 5) + ++#define HSWEQ_DCN_PIXEL_RATE_REG_LIST(blk, inst) \ ++ SRII(PIXEL_RATE_CNTL, blk, inst), \ ++ SRII(PHYPLL_PIXEL_RATE_CNTL, blk, inst) ++ + #define HWSEQ_PIXEL_RATE_REG_LIST(blk) \ + SRII(PIXEL_RATE_CNTL, blk, 0), \ + SRII(PIXEL_RATE_CNTL, blk, 1), \ +@@ -151,7 +155,10 @@ + SR(DCCG_GATE_DISABLE_CNTL2), \ + SR(DCFCLK_CNTL),\ + SR(DCFCLK_CNTL), \ +- SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ ++ SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) ++ ++ ++#define MMHUB_DCN_REG_LIST()\ + /* todo: get these from GVM instead of reading registers ourselves */\ + MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\ + MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\ +@@ -166,10 +173,14 @@ + MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\ + MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR) + ++ + #define HWSEQ_DCN1_REG_LIST()\ + HWSEQ_DCN_REG_LIST(), \ +- HWSEQ_PIXEL_RATE_REG_LIST(OTG), \ +- HWSEQ_PHYPLL_REG_LIST(OTG), \ ++ MMHUB_DCN_REG_LIST(), \ ++ HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ ++ HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ ++ HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ ++ HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ + SR(DCHUBBUB_SDPIF_FB_BASE),\ + SR(DCHUBBUB_SDPIF_FB_OFFSET),\ + SR(DCHUBBUB_SDPIF_AGP_BASE),\ +@@ -202,8 +213,12 @@ + #if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #define HWSEQ_DCN2_REG_LIST()\ + HWSEQ_DCN_REG_LIST(), \ +- HWSEQ_PIXEL_RATE_REG_LIST(OTG), \ +- HWSEQ_PHYPLL_REG_LIST(OTG), \ ++ HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ ++ HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ ++ HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ ++ HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ ++ HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 4), \ ++ HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 5), \ + SR(MICROSECOND_TIME_BASE_DIV), \ + SR(MILLISECOND_TIME_BASE_DIV), \ + SR(DISPCLK_FREQ_CHANGE_CNTL), \ +-- +2.17.1 + |