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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3500-Revert-drm-amd-display-add-global-master-update-lock.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3500-Revert-drm-amd-display-add-global-master-update-lock.patch150
1 files changed, 150 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3500-Revert-drm-amd-display-add-global-master-update-lock.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3500-Revert-drm-amd-display-add-global-master-update-lock.patch
new file mode 100644
index 00000000..8cd611e1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3500-Revert-drm-amd-display-add-global-master-update-lock.patch
@@ -0,0 +1,150 @@
+From 98da34992358a815deebf1e899d6f7915e7539f2 Mon Sep 17 00:00:00 2001
+From: David Francis <David.Francis@amd.com>
+Date: Thu, 23 May 2019 14:06:08 -0400
+Subject: [PATCH 3500/4256] Revert "drm/amd/display: add global master update
+ lock for DCN2"
+
+This reverts commit 55a6f5bbcf00a49565946c0a9b8c716313dc6c05.
+
+This commit was accidentally promoted twice
+
+Signed-off-by: David Francis <David.Francis@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+---
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 4 --
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 63 +------------------
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h | 3 -
+ .../amd/display/dc/inc/hw/timing_generator.h | 2 -
+ 4 files changed, 1 insertion(+), 71 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 75c670d4443a..abbae9fb8eff 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -811,10 +811,6 @@ enum dc_status dcn20_enable_stream_timing(
+ pipe_ctx->stream->signal,
+ true);
+
+- if (pipe_ctx->stream_res.tg->funcs->setup_global_lock)
+- pipe_ctx->stream_res.tg->funcs->setup_global_lock(
+- pipe_ctx->stream_res.tg);
+-
+ if (odm_pipe)
+ odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
+ odm_pipe->stream_res.opp,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+index 99070e93020b..2137e2be2140 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+@@ -333,65 +333,6 @@ void optc2_triplebuffer_unlock(struct timing_generator *optc)
+
+ }
+
+-
+-void optc2_setup_global_lock(struct timing_generator *optc)
+-{
+- struct optc *optc1 = DCN10TG_FROM_TG(optc);
+- uint32_t v_blank_start = 0;
+- uint32_t h_blank_start = 0, h_total = 0;
+-
+- REG_SET(OTG_GLOBAL_CONTROL1, 0, MASTER_UPDATE_LOCK_DB_EN, 1);
+-
+- REG_SET(OTG_GLOBAL_CONTROL2, 0, DIG_UPDATE_LOCATION, 20);
+-
+- REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, &v_blank_start);
+-
+- REG_GET(OTG_H_BLANK_START_END, OTG_H_BLANK_START, &h_blank_start);
+-
+- REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &h_total);
+- REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
+- MASTER_UPDATE_LOCK_DB_X,
+- h_blank_start - 200 - 1,
+- MASTER_UPDATE_LOCK_DB_Y,
+- v_blank_start - 1);
+-}
+-
+-void optc2_lock_global(struct timing_generator *optc)
+-{
+- struct optc *optc1 = DCN10TG_FROM_TG(optc);
+-
+- REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1);
+-
+- REG_SET(OTG_GLOBAL_CONTROL0, 0,
+- OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
+- REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
+- OTG_MASTER_UPDATE_LOCK, 1);
+-
+- /* Should be fast, status does not update on maximus */
+- if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
+- REG_WAIT(OTG_MASTER_UPDATE_LOCK,
+- UPDATE_LOCK_STATUS, 1,
+- 1, 10);
+-}
+-
+-void optc2_lock(struct timing_generator *optc)
+-{
+- struct optc *optc1 = DCN10TG_FROM_TG(optc);
+-
+- REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0);
+-
+- REG_SET(OTG_GLOBAL_CONTROL0, 0,
+- OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
+- REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
+- OTG_MASTER_UPDATE_LOCK, 1);
+-
+- /* Should be fast, status does not update on maximus */
+- if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
+- REG_WAIT(OTG_MASTER_UPDATE_LOCK,
+- UPDATE_LOCK_STATUS, 1,
+- 1, 10);
+-}
+-
+ void optc2_lock_doublebuffer_enable(struct timing_generator *optc)
+ {
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
+@@ -486,10 +427,8 @@ static struct timing_generator_funcs dcn20_tg_funcs = {
+ .triplebuffer_lock = optc2_triplebuffer_lock,
+ .triplebuffer_unlock = optc2_triplebuffer_unlock,
+ .disable_reset_trigger = optc1_disable_reset_trigger,
+- .lock = optc2_lock,
++ .lock = optc1_lock,
+ .unlock = optc1_unlock,
+- .lock_global = optc2_lock_global,
+- .setup_global_lock = optc2_setup_global_lock,
+ .lock_doublebuffer_enable = optc2_lock_doublebuffer_enable,
+ .lock_doublebuffer_disable = optc2_lock_doublebuffer_disable,
+ .enable_optc_clock = optc1_enable_optc_clock,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
+index 47cb4de1564c..32a58431fd09 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
+@@ -106,9 +106,6 @@ void optc2_get_optc_source(struct timing_generator *optc,
+
+ void optc2_triplebuffer_lock(struct timing_generator *optc);
+ void optc2_triplebuffer_unlock(struct timing_generator *optc);
+-void optc2_lock(struct timing_generator *optc);
+-void optc2_lock_global(struct timing_generator *optc);
+-void optc2_setup_global_lock(struct timing_generator *optc);
+ void optc2_lock_doublebuffer_disable(struct timing_generator *optc);
+ void optc2_lock_doublebuffer_enable(struct timing_generator *optc);
+ void optc2_program_manual_trigger(struct timing_generator *optc);
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+index f607ef24c766..e0713d6d6c8d 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+@@ -189,10 +189,8 @@ struct timing_generator_funcs {
+ bool (*did_triggered_reset_occur)(struct timing_generator *tg);
+ void (*setup_global_swap_lock)(struct timing_generator *tg,
+ const struct dcp_gsl_params *gsl_params);
+- void (*setup_global_lock)(struct timing_generator *tg);
+ void (*unlock)(struct timing_generator *tg);
+ void (*lock)(struct timing_generator *tg);
+- void (*lock_global)(struct timing_generator *tg);
+ void (*lock_doublebuffer_disable)(struct timing_generator *tg);
+ void (*lock_doublebuffer_enable)(struct timing_generator *tg);
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+--
+2.17.1
+