diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3475-drm-amd-powerplay-get-bootup-fclk-value.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3475-drm-amd-powerplay-get-bootup-fclk-value.patch | 71 |
1 files changed, 71 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3475-drm-amd-powerplay-get-bootup-fclk-value.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3475-drm-amd-powerplay-get-bootup-fclk-value.patch new file mode 100644 index 00000000..b9d7e2e7 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3475-drm-amd-powerplay-get-bootup-fclk-value.patch @@ -0,0 +1,71 @@ +From 778aca4eea500d4be59e80f73a2c5994459f60dd Mon Sep 17 00:00:00 2001 +From: Evan Quan <evan.quan@amd.com> +Date: Fri, 16 Aug 2019 13:47:01 +0800 +Subject: [PATCH 3475/4256] drm/amd/powerplay: get bootup fclk value + +This is available with firmwareinfo table v3.2 or later. + +Change-Id: I223edf3c616b9e3e2527c752214fef5ab53d1cea +Signed-off-by: Evan Quan <evan.quan@amd.com> +Reviewed-by: Kevin Wang <kevin1.wang@amd.com> +--- + .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++ + drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 21 +++++++++++++++++++ + 2 files changed, 24 insertions(+) + +diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +index fc59d9686e61..e80c81552d29 100644 +--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h ++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +@@ -222,6 +222,9 @@ struct smu_bios_boot_up_values + uint16_t vdd_gfx; + uint8_t cooling_id; + uint32_t pp_table_id; ++ uint32_t format_revision; ++ uint32_t content_revision; ++ uint32_t fclk; + }; + + enum smu_table_id +diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c +index 4cdbed3b7a83..16d7768dca9b 100644 +--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c ++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c +@@ -570,6 +570,9 @@ int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu) + smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id; + } + ++ smu->smu_table.boot_values.format_revision = header->format_revision; ++ smu->smu_table.boot_values.content_revision = header->content_revision; ++ + return 0; + } + +@@ -649,6 +652,24 @@ static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu) + output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input; + smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000; + ++ if ((smu->smu_table.boot_values.format_revision == 3) && ++ (smu->smu_table.boot_values.content_revision >= 2)) { ++ memset(&input, 0, sizeof(input)); ++ input.clk_id = SMU11_SYSPLL1_0_FCLK_ID; ++ input.syspll_id = SMU11_SYSPLL1_2_ID; ++ input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ; ++ index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1, ++ getsmuclockinfo); ++ ++ ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index, ++ (uint32_t *)&input); ++ if (ret) ++ return -EINVAL; ++ ++ output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input; ++ smu->smu_table.boot_values.fclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000; ++ } ++ + return 0; + } + +-- +2.17.1 + |