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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3435-drm-amd-display-Add-and-refine-DSC-logs-in-enable-se.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3435-drm-amd-display-Add-and-refine-DSC-logs-in-enable-se.patch135
1 files changed, 135 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3435-drm-amd-display-Add-and-refine-DSC-logs-in-enable-se.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3435-drm-amd-display-Add-and-refine-DSC-logs-in-enable-se.patch
new file mode 100644
index 00000000..48545a13
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3435-drm-amd-display-Add-and-refine-DSC-logs-in-enable-se.patch
@@ -0,0 +1,135 @@
+From 9e8f7a0ff18ca301b3be17010787a9839d23586c Mon Sep 17 00:00:00 2001
+From: Nikola Cornij <nikola.cornij@amd.com>
+Date: Thu, 25 Jul 2019 18:46:54 -0400
+Subject: [PATCH 3435/4256] drm/amd/display: Add and refine DSC logs in enable
+ sequence
+
+[why]
+Some logs messages were not precise and some new log messages
+were needed after "get packed PPS" function was introduced
+
+Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
+Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../drm/amd/display/dc/core/dc_link_hwss.c | 34 ++++++++++++++-----
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 14 +++++---
+ 2 files changed, 35 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+index af65071b6cf5..35c5467e60e8 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+@@ -342,10 +342,22 @@ void dp_retrain_link_dp_test(struct dc_link *link,
+ static void dsc_optc_config_log(struct display_stream_compressor *dsc,
+ struct dsc_optc_config *config)
+ {
+- DC_LOG_DSC("Setting optc DSC config at DSC inst %d", dsc->inst);
+- DC_LOG_DSC("\n\tbytes_per_pixel %d\n\tis_pixel_format_444 %d\n\tslice_width %d",
+- config->bytes_per_pixel,
+- config->is_pixel_format_444, config->slice_width);
++ uint32_t precision = 1 << 28;
++ uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision;
++ uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision;
++ uint64_t ll_bytes_per_pix_fraq = bytes_per_pixel_mod;
++
++ /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC
++ * bits per pixel precision is 1/16th of a pixel, which means bytes per pixel precision is
++ * 1/16/8 = 1/128 of a byte, or 0.0078125 decimal
++ */
++ ll_bytes_per_pix_fraq *= 10000000;
++ ll_bytes_per_pix_fraq /= precision;
++
++ DC_LOG_DSC("\tbytes_per_pixel 0x%08x (%d.%07d)",
++ config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq);
++ DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444);
++ DC_LOG_DSC("\tslice_width %d", config->slice_width);
+ }
+
+ static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)
+@@ -400,17 +412,21 @@ void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
+
+ optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
+
+- dsc_optc_config_log(dsc, &dsc_optc_cfg);
+ /* Enable DSC in encoder */
+- if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment))
++ if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++ DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id);
++ dsc_optc_config_log(dsc, &dsc_optc_cfg);
+ pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc,
+ optc_dsc_mode,
+ dsc_optc_cfg.bytes_per_pixel,
+ dsc_optc_cfg.slice_width);
+
+ /* PPS SDP is set elsewhere because it has to be done after DIG FE is connected to DIG BE */
++ }
+
+ /* Enable DSC in OPTC */
++ DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
++ dsc_optc_config_log(dsc, &dsc_optc_cfg);
+ pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,
+ optc_dsc_mode,
+ dsc_optc_cfg.bytes_per_pixel,
+@@ -482,13 +498,15 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable)
+ dsc_cfg.color_depth = stream->timing.display_color_depth;
+ dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
+
++ DC_LOG_DSC(" ");
+ dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]);
+- if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment))
++ if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++ DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id);
+ pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
+ pipe_ctx->stream_res.stream_enc,
+ true,
+ &dsc_packed_pps[0]);
+-
++ }
+ } else {
+ /* disable DSC PPS in stream encoder */
+ if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+index 808f4d154e61..379c9e4ac63b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+@@ -175,11 +175,13 @@ static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const st
+
+ static void dsc_config_log(struct display_stream_compressor *dsc, const struct dsc_config *config)
+ {
+- DC_LOG_DSC("\n\tnum_slices_h %d\n\tnum_slices_v %d\n\tbits_per_pixel %d\n\tcolor_depth %d",
+- config->dc_dsc_cfg.num_slices_h,
+- config->dc_dsc_cfg.num_slices_v,
++ DC_LOG_DSC("\tnum_slices_h %d", config->dc_dsc_cfg.num_slices_h);
++ DC_LOG_DSC("\tnum_slices_v %d", config->dc_dsc_cfg.num_slices_v);
++ DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)",
+ config->dc_dsc_cfg.bits_per_pixel,
+- config->color_depth);
++ config->dc_dsc_cfg.bits_per_pixel / 16,
++ ((config->dc_dsc_cfg.bits_per_pixel % 16) * 10000) / 16);
++ DC_LOG_DSC("\tcolor_depth %d", config->color_depth);
+ }
+
+ static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
+@@ -188,6 +190,7 @@ static void dsc2_set_config(struct display_stream_compressor *dsc, const struct
+ bool is_config_ok;
+ struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
+
++ DC_LOG_DSC(" ");
+ DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);
+ dsc_config_log(dsc, dsc_cfg);
+ is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg);
+@@ -204,8 +207,9 @@ static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const str
+ struct dsc_reg_values dsc_reg_vals;
+ struct dsc_optc_config dsc_optc_cfg;
+
+- DC_LOG_DSC("Packed DSC PPS for DSC Config:");
++ DC_LOG_DSC("Getting packed DSC PPS for DSC Config:");
+ dsc_config_log(dsc, dsc_cfg);
++ DC_LOG_DSC("DSC Picture Parameter Set (PPS):");
+ is_config_ok = dsc_prepare_config(dsc_cfg, &dsc_reg_vals, &dsc_optc_cfg);
+ ASSERT(is_config_ok);
+ drm_dsc_pps_payload_pack((struct drm_dsc_picture_parameter_set *)dsc_packed_pps, &dsc_reg_vals.pps);
+--
+2.17.1
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-20 01:54:52 +0000