diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3432-drm-amd-display-Add-enum-for-H-timing-divider-mode.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3432-drm-amd-display-Add-enum-for-H-timing-divider-mode.patch | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3432-drm-amd-display-Add-enum-for-H-timing-divider-mode.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3432-drm-amd-display-Add-enum-for-H-timing-divider-mode.patch new file mode 100644 index 00000000..6bccaa15 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3432-drm-amd-display-Add-enum-for-H-timing-divider-mode.patch @@ -0,0 +1,63 @@ +From aa03504f3858ddad3064ce53ae4f836c285251ec Mon Sep 17 00:00:00 2001 +From: Qingqing Zhuo <qingqing.zhuo@amd.com> +Date: Tue, 23 Jul 2019 12:24:24 -0400 +Subject: [PATCH 3432/4256] drm/amd/display: Add enum for H-timing divider mode + +Add h_timing_div_mode enum to better reflect possible register +values. Replace previously programmed values with enum + +Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com> +Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 9 +++++---- + drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h | 5 +++++ + 2 files changed, 10 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c +index a96e73baefbd..66d8f6410b53 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c +@@ -154,7 +154,7 @@ void optc1_program_timing( + uint32_t h_sync_polarity, v_sync_polarity; + uint32_t start_point = 0; + uint32_t field_num = 0; +- uint32_t h_div_2; ++ enum h_timing_div_mode h_div = H_TIMING_NO_DIV; + + struct optc *optc1 = DCN10TG_FROM_TG(optc); + +@@ -285,10 +285,11 @@ void optc1_program_timing( + * of stereo handled in explicit call + */ + +- h_div_2 = optc1_is_two_pixels_per_containter(&patched_crtc_timing); +- REG_UPDATE(OTG_H_TIMING_CNTL, +- OTG_H_TIMING_DIV_BY2, h_div_2 || optc1->opp_count == 2); ++ if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2) ++ h_div = H_TIMING_DIV_BY2; + ++ REG_UPDATE(OTG_H_TIMING_CNTL, ++ OTG_H_TIMING_DIV_BY2, h_div); + } + + void optc1_set_vtg_params(struct timing_generator *optc, +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +index 1f83cb7c7dd4..f607ef24c766 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +@@ -96,6 +96,11 @@ enum crc_selection { + INTERSECT_WINDOW_NOT_A_NOT_B, + }; + ++enum h_timing_div_mode { ++ H_TIMING_NO_DIV, ++ H_TIMING_DIV_BY2, ++}; ++ + struct crc_params { + /* Regions used to calculate CRC*/ + uint16_t windowa_x_start; +-- +2.17.1 + |