diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3419-drm-amd-display-Remove-duplicate-interface-for-progr.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3419-drm-amd-display-Remove-duplicate-interface-for-progr.patch | 371 |
1 files changed, 371 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3419-drm-amd-display-Remove-duplicate-interface-for-progr.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3419-drm-amd-display-Remove-duplicate-interface-for-progr.patch new file mode 100644 index 00000000..40efbe58 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3419-drm-amd-display-Remove-duplicate-interface-for-progr.patch @@ -0,0 +1,371 @@ +From c1b9fbe9b19ccfc47c880dac1ac65757584a8fa5 Mon Sep 17 00:00:00 2001 +From: Julian Parkin <julian.parkin@amd.com> +Date: Mon, 15 Jul 2019 12:16:01 -0400 +Subject: [PATCH 3419/4256] drm/amd/display: Remove duplicate interface for + programming FB + +[Why] +There are currently two interfaces for exactly the same thing: +hupb_update_dchub in hupb and update_dchub in hubbub. The hubbub +version is currently unused past dcn10, largely because the call +from the dcn10 hardware sequencer does not call through the +interface, so the hupb interface was used instead. This is +confusing because of the duplicate code, the unused functions, +and the fact that more that one block currently owns this set +of registers. + +[How] +Remove the hubp interface entirely, as well as the register +declarations that are not longer needed because of this. Change +the call site to always call the hubbub version through the +interface. Fix the update_dchub function in dcn20_hubbub.c to +program the correct registers for dcn20. + +Signed-off-by: Julian Parkin <julian.parkin@amd.com> +Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +--- + .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 24 ------ + .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 10 +-- + .../drm/amd/display/dc/dcn20/dcn20_hubbub.c | 81 +++++++++++-------- + .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 76 ----------------- + .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 16 ---- + drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 3 - + 6 files changed, 50 insertions(+), 160 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h +index 344e446e337d..91116b3d4b48 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h +@@ -125,8 +125,6 @@ + SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, HUBPREQ, id),\ + SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, HUBPREQ, id),\ + SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, HUBPREQ, id),\ +- SR(DCHUBBUB_SDPIF_FB_BASE),\ +- SR(DCHUBBUB_SDPIF_FB_OFFSET),\ + SRI(CURSOR_SETTINS, HUBPREQ, id), \ + SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \ + SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \ +@@ -226,14 +224,6 @@ + uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB; \ + uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR; \ + uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR; \ +- uint32_t DCHUBBUB_SDPIF_FB_BASE; \ +- uint32_t DCHUBBUB_SDPIF_FB_OFFSET; \ +- uint32_t DCN_VM_FB_LOCATION_TOP; \ +- uint32_t DCN_VM_FB_LOCATION_BASE; \ +- uint32_t DCN_VM_FB_OFFSET; \ +- uint32_t DCN_VM_AGP_BASE; \ +- uint32_t DCN_VM_AGP_BOT; \ +- uint32_t DCN_VM_AGP_TOP; \ + uint32_t CURSOR_SETTINS; \ + uint32_t CURSOR_SETTINGS; \ + uint32_t CURSOR_SURFACE_ADDRESS_HIGH; \ +@@ -417,8 +407,6 @@ + HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mask_sh),\ +- HUBP_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh),\ +- HUBP_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\ +@@ -593,18 +581,6 @@ + type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB;\ + type MC_VM_SYSTEM_APERTURE_LOW_ADDR;\ + type MC_VM_SYSTEM_APERTURE_HIGH_ADDR;\ +- type SDPIF_FB_TOP;\ +- type SDPIF_FB_BASE;\ +- type SDPIF_FB_OFFSET;\ +- type SDPIF_AGP_BASE;\ +- type SDPIF_AGP_BOT;\ +- type SDPIF_AGP_TOP;\ +- type FB_TOP;\ +- type FB_BASE;\ +- type FB_OFFSET;\ +- type AGP_BASE;\ +- type AGP_BOT;\ +- type AGP_TOP;\ + type DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\ + type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\ + type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\ +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index 86f874bddd84..8fd2d51477ea 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -2856,14 +2856,10 @@ static void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) + + static void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data) + { +- if (hws->ctx->dc->res_pool->hubbub != NULL) { +- struct hubp *hubp = hws->ctx->dc->res_pool->hubps[0]; ++ struct hubbub *hubbub = hws->ctx->dc->res_pool->hubbub; + +- if (hubp->funcs->hubp_update_dchub) +- hubp->funcs->hubp_update_dchub(hubp, dh_data); +- else +- hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data); +- } ++ /* In DCN, this programming sequence is owned by the hubbub */ ++ hubbub->funcs->update_dchub(hubbub, dh_data); + } + + static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx) +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c +index cd101bbd8163..f13e039f8ef4 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c +@@ -398,54 +398,67 @@ void hubbub2_update_dchub(struct hubbub *hubbub, + { + struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); + +- if (REG(DCHUBBUB_SDPIF_FB_TOP) == 0) { +- ASSERT(false); +- /*should not come here*/ ++ if (REG(DCN_VM_FB_LOCATION_TOP) == 0) + return; +- } +- /* TODO: port code from dal2 */ ++ + switch (dh_data->fb_mode) { + case FRAME_BUFFER_MODE_ZFB_ONLY: + /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/ +- REG_UPDATE(DCHUBBUB_SDPIF_FB_TOP, +- SDPIF_FB_TOP, 0); +- +- REG_UPDATE(DCHUBBUB_SDPIF_FB_BASE, +- SDPIF_FB_BASE, 0x0FFFF); +- +- REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, +- SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22); +- +- REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, +- SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22); +- +- REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, +- SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr + +- dh_data->zfb_size_in_byte - 1) >> 22); ++ REG_UPDATE(DCN_VM_FB_LOCATION_TOP, ++ FB_TOP, 0); ++ ++ REG_UPDATE(DCN_VM_FB_LOCATION_BASE, ++ FB_BASE, 0xFFFFFF); ++ ++ /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/ ++ REG_UPDATE(DCN_VM_AGP_BASE, ++ AGP_BASE, dh_data->zfb_phys_addr_base >> 24); ++ ++ /*This field defines the bottom range of the AGP aperture and represents the 24*/ ++ /*MSBs, bits [47:24] of the 48 address bits*/ ++ REG_UPDATE(DCN_VM_AGP_BOT, ++ AGP_BOT, dh_data->zfb_mc_base_addr >> 24); ++ ++ /*This field defines the top range of the AGP aperture and represents the 24*/ ++ /*MSBs, bits [47:24] of the 48 address bits*/ ++ REG_UPDATE(DCN_VM_AGP_TOP, ++ AGP_TOP, (dh_data->zfb_mc_base_addr + ++ dh_data->zfb_size_in_byte - 1) >> 24); + break; + case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL: + /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ + +- REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, +- SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22); ++ /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/ ++ REG_UPDATE(DCN_VM_AGP_BASE, ++ AGP_BASE, dh_data->zfb_phys_addr_base >> 24); + +- REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, +- SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22); ++ /*This field defines the bottom range of the AGP aperture and represents the 24*/ ++ /*MSBs, bits [47:24] of the 48 address bits*/ ++ REG_UPDATE(DCN_VM_AGP_BOT, ++ AGP_BOT, dh_data->zfb_mc_base_addr >> 24); + +- REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, +- SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr + +- dh_data->zfb_size_in_byte - 1) >> 22); ++ /*This field defines the top range of the AGP aperture and represents the 24*/ ++ /*MSBs, bits [47:24] of the 48 address bits*/ ++ REG_UPDATE(DCN_VM_AGP_TOP, ++ AGP_TOP, (dh_data->zfb_mc_base_addr + ++ dh_data->zfb_size_in_byte - 1) >> 24); + break; + case FRAME_BUFFER_MODE_LOCAL_ONLY: +- /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ +- REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, +- SDPIF_AGP_BASE, 0); ++ /*Should not touch FB LOCATION (should be done by VBIOS)*/ ++ ++ /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/ ++ REG_UPDATE(DCN_VM_AGP_BASE, ++ AGP_BASE, 0); + +- REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, +- SDPIF_AGP_BOT, 0X03FFFF); ++ /*This field defines the bottom range of the AGP aperture and represents the 24*/ ++ /*MSBs, bits [47:24] of the 48 address bits*/ ++ REG_UPDATE(DCN_VM_AGP_BOT, ++ AGP_BOT, 0xFFFFFF); + +- REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, +- SDPIF_AGP_TOP, 0); ++ /*This field defines the top range of the AGP aperture and represents the 24*/ ++ /*MSBs, bits [47:24] of the 48 address bits*/ ++ REG_UPDATE(DCN_VM_AGP_TOP, ++ AGP_TOP, 0); + break; + default: + break; +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c +index 487de87b03eb..ac01e636ae27 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c +@@ -40,81 +40,6 @@ + #define FN(reg_name, field_name) \ + hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name + +-void hubp2_update_dchub( +- struct hubp *hubp, +- struct dchub_init_data *dh_data) +-{ +- struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); +- if (REG(DCN_VM_FB_LOCATION_TOP) == 0) +- return; +- +- switch (dh_data->fb_mode) { +- case FRAME_BUFFER_MODE_ZFB_ONLY: +- /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/ +- REG_UPDATE(DCN_VM_FB_LOCATION_TOP, +- FB_TOP, 0); +- +- REG_UPDATE(DCN_VM_FB_LOCATION_BASE, +- FB_BASE, 0xFFFFFF); +- +- /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/ +- REG_UPDATE(DCN_VM_AGP_BASE, +- AGP_BASE, dh_data->zfb_phys_addr_base >> 24); +- +- /*This field defines the bottom range of the AGP aperture and represents the 24*/ +- /*MSBs, bits [47:24] of the 48 address bits*/ +- REG_UPDATE(DCN_VM_AGP_BOT, +- AGP_BOT, dh_data->zfb_mc_base_addr >> 24); +- +- /*This field defines the top range of the AGP aperture and represents the 24*/ +- /*MSBs, bits [47:24] of the 48 address bits*/ +- REG_UPDATE(DCN_VM_AGP_TOP, +- AGP_TOP, (dh_data->zfb_mc_base_addr + +- dh_data->zfb_size_in_byte - 1) >> 24); +- break; +- case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL: +- /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ +- +- /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/ +- REG_UPDATE(DCN_VM_AGP_BASE, +- AGP_BASE, dh_data->zfb_phys_addr_base >> 24); +- +- /*This field defines the bottom range of the AGP aperture and represents the 24*/ +- /*MSBs, bits [47:24] of the 48 address bits*/ +- REG_UPDATE(DCN_VM_AGP_BOT, +- AGP_BOT, dh_data->zfb_mc_base_addr >> 24); +- +- /*This field defines the top range of the AGP aperture and represents the 24*/ +- /*MSBs, bits [47:24] of the 48 address bits*/ +- REG_UPDATE(DCN_VM_AGP_TOP, +- AGP_TOP, (dh_data->zfb_mc_base_addr + +- dh_data->zfb_size_in_byte - 1) >> 24); +- break; +- case FRAME_BUFFER_MODE_LOCAL_ONLY: +- /*Should not touch FB LOCATION (should be done by VBIOS)*/ +- +- /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/ +- REG_UPDATE(DCN_VM_AGP_BASE, +- AGP_BASE, 0); +- +- /*This field defines the bottom range of the AGP aperture and represents the 24*/ +- /*MSBs, bits [47:24] of the 48 address bits*/ +- REG_UPDATE(DCN_VM_AGP_BOT, +- AGP_BOT, 0xFFFFFF); +- +- /*This field defines the top range of the AGP aperture and represents the 24*/ +- /*MSBs, bits [47:24] of the 48 address bits*/ +- REG_UPDATE(DCN_VM_AGP_TOP, +- AGP_TOP, 0); +- break; +- default: +- break; +- } +- +- dh_data->dchub_initialzied = true; +- dh_data->dchub_info_valid = false; +-} +- + void hubp2_set_vm_system_aperture_settings(struct hubp *hubp, + struct vm_system_aperture_param *apt) + { +@@ -1321,7 +1246,6 @@ static struct hubp_funcs dcn20_hubp_funcs = { + .hubp_set_vm_system_aperture_settings = hubp2_set_vm_system_aperture_settings, + .set_blank = hubp2_set_blank, + .dcc_control = hubp2_dcc_control, +- .hubp_update_dchub = hubp2_update_dchub, + .mem_program_viewport = min_set_viewport, + .set_cursor_attributes = hubp2_cursor_set_attributes, + .set_cursor_position = hubp2_cursor_set_position, +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h +index 1c53af4811e8..924699e5f443 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h +@@ -38,12 +38,6 @@ + SRI(PREFETCH_SETTINGS_C, HUBPREQ, id),\ + SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, HUBPREQ, id),\ + SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, HUBPREQ, id),\ +- SR(DCN_VM_FB_LOCATION_TOP),\ +- SR(DCN_VM_FB_LOCATION_BASE),\ +- SR(DCN_VM_FB_OFFSET),\ +- SR(DCN_VM_AGP_BASE),\ +- SR(DCN_VM_AGP_BOT),\ +- SR(DCN_VM_AGP_TOP),\ + SRI(CURSOR_SETTINGS, HUBPREQ, id), \ + SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \ + SRI(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \ +@@ -82,12 +76,6 @@ + HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\ +- HUBP_SF(DCN_VM_FB_LOCATION_TOP, FB_TOP, mask_sh),\ +- HUBP_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE, mask_sh),\ +- HUBP_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh),\ +- HUBP_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh),\ +- HUBP_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh),\ +- HUBP_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh),\ + HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \ + HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ + HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ +@@ -222,10 +210,6 @@ void hubp2_setup_interdependent( + void hubp2_vready_at_or_After_vsync(struct hubp *hubp, + struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest); + +-void hubp2_update_dchub( +- struct hubp *hubp, +- struct dchub_init_data *dh_data); +- + void hubp2_cursor_set_attributes( + struct hubp *hubp, + const struct dc_cursor_attributes *attr); +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +index 61cd4f8752c3..4993f134e747 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +@@ -111,9 +111,6 @@ struct hubp_funcs { + + bool (*hubp_is_flip_pending)(struct hubp *hubp); + +- void (*hubp_update_dchub)(struct hubp *hubp, +- struct dchub_init_data *dh_data); +- + void (*set_blank)(struct hubp *hubp, bool blank); + void (*set_hubp_blank_en)(struct hubp *hubp, bool blank); + +-- +2.17.1 + |